@llvm/pr-subscribers-backend-risc-v

Author: Alex Bradbury (asb)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cppindex de830666d89b8..b53f2808eeb41 100644--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp@@ -2319,6 +2319,10 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,   if (getLegalZfaFPImm(Imm, VT) >= 0)     return true;+  // Some constants can be produced by fli+fneg.+  if (Imm.isNegative() && getLegalZfaFPImm(-Imm, VT) >= 0)+    return true;+   // Cannot create a 64 bit floating-point immediate value for rv32.   if (Subtarget.getXLen() < VT.getScalarSizeInBits()) {     // td can handle +0.0 or -0.0 already.

I removed this in#108316. isLegalFPImm is not supposed to be in sync with lowerConstantFP. lowerConstantFP handles things that aren't legal.

Thanks for the reference. How would you define "legal" constants for isFPImmLegal because by my reading of the function, it's currently counting anything that can be handled with two instructions (e.g. -0.0 via fmv x0 then fneg, and FP values with bit patterns that can be loaded with a single int instruction then fmv).

Thanks for the reference. How would you define "legal" constants for isFPImmLegal because by my reading of the function, it's currently counting anything that can be handled with two instructions (e.g. -0.0 via fmv x0 then fneg, and FP values with bit patterns that can be loaded with a single int instruction then fmv).

I thought "legal" was anything that was handled by the code incase ISD::ConstantFP in RISCVISelDAGToDAG.cpp. Which would be anything that is "legal" to reach isel.

But looking closer, LegalizeDAG.cpp only checksisLegalFPImm inExpandNode which would be after LowerConstantFP gets called. So maybe we can say things in LowerConstantFP are "legal".