diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.tdindex bd480aacc539e..214fd8158a679 100644--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td@@ -54,6 +54,12 @@ def : WriteRes<WriteShiftImm32, [Andes45ALU]>; def : WriteRes<WriteShiftReg, [Andes45ALU]>; def : WriteRes<WriteShiftReg32, [Andes45ALU]>;+// Short forward branch+def : WriteRes<WriteSFB, [Andes45ALU]> {+  let Latency = 1;+  let NumMicroOps = 2;+}+ // Branching def : WriteRes<WriteJmp, [Andes45ALU]>; def : WriteRes<WriteJal, [Andes45ALU]>;@@ -231,6 +237,8 @@ def : ReadAdvance<ReadShiftImm, 0>; def : ReadAdvance<ReadShiftImm32, 0>; def : ReadAdvance<ReadShiftReg, 0>; def : ReadAdvance<ReadShiftReg32, 0>;+def : ReadAdvance<ReadSFBJmp, 0>;+def : ReadAdvance<ReadSFBALU, 0>; def : ReadAdvance<ReadJalr, 0>; def : ReadAdvance<ReadJmp, 0>; def : ReadAdvance<ReadIMul, 0>;@@ -328,7 +336,6 @@ def : ReadAdvance<ReadCSR, 0>; //===----------------------------------------------------------------------===// // Unsupported extensions defm : UnsupportedSchedQ;-defm : UnsupportedSchedSFB; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; defm : UnsupportedSchedXSfvfnrclipxfqf;