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[NFC][AMDGPU] Fix a test issue in
llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll backend:AMDGPU #149826 openedJul 21, 2025 byshiltianLoading…
[PatternMatch] Add support for capture-and-match (NFC) llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:transforms
#149825 openedJul 21, 2025 bynikicLoading…
A test PR for #140694 while waiting for #149110 to be accepted
#149824 openedJul 21, 2025 bychrisjbris • Draft
[compiler-rt][MSVC] Conditionally remove emupac.cpp for msvc compiler-rt:builtins compiler-rt
#149823 openedJul 21, 2025 byzacklj89Loading…
[X86] canCreateUndefOrPoisonForTargetNode - SSE PINSR/PEXTR vector element insert/extract are never out of bounds backend:X86
#149822 openedJul 21, 2025 byRKSimonLoading…
[Clang][Driver][ARM] Forward'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clangClang issues not falling into any other category
-Os and-Oz as multilib flags clang:driver #149819 openedJul 21, 2025 byvhscamposLoading…
[GVNSink] Do not sink lifetimes of different allocas llvm:transforms
#149818 openedJul 21, 2025 bynikicLoading…
[AMDGPU] Optimize rotate/funnel shift pattern matching in instruction selection backend:AMDGPU llvm:globalisel llvm:transforms
#149817 openedJul 21, 2025 byaleksandar-amdLoading…
[DebugInfo] Remove intrinsic-flavours of findDbgUsers backend:AMDGPU clang:codegenIR generation bugs: mangling, exceptions, etc. clangClang issues not falling into any other category coroutinesC++20 coroutines debuginfo llvm:codegen llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:transforms
#149816 openedJul 21, 2025 byjmorseLoading…
[CodeGen] Add a pass for testing finalizeBundle backend:AMDGPU llvm:codegen
#149813 openedJul 21, 2025 byjayfoadLoading…
[clang][bytecode] Use OptPrimType instead of std::optional<PrimType> clang:bytecodeIssues for the clang bytecode constexpr interpreter clang:frontendLanguage frontend issues, e.g. anything involving "Sema" clangClang issues not falling into any other category
#149812 openedJul 21, 2025 bytbaederrLoading…
[PowerPC] Add assembly directives to change endianness backend:PowerPC mcMachine (object) code
#149811 openedJul 21, 2025 byDanilaZhebryakovLoading…
[MLIR][AArch64] Refactor lowering of vector.contract to Neon I8MM mlir:neon mlir
#149810 openedJul 21, 2025 bymomchil-velikovLoading…
[mlir][NFC] UseMLIR Core Infrastructure mlir:gpu mlir:linalg mlir:llvm mlir:openacc mlir:openmp mlir:scf mlir:shape mlir openacc
hasOneBlock instead ofllvm::hasSingleElement(region) flang:openmp mlir:affine mlir:core #149809 openedJul 21, 2025 byCoTinkerLoading…
[AggressiveInstCombine] Support store merge with non-consecutive parts llvm:transforms
#149807 openedJul 21, 2025 bynikicLoading…
[CodeGen] Remove FinalizeMachineBundles pass backend:AMDGPU llvm:codegen
#149806 openedJul 21, 2025 byjayfoadLoading…
[mlir][mesh] removing partial/reduction axes from mesh.sharding mlir:linalg mlir
#149805 openedJul 21, 2025 byfschlimbLoading…
[mlir] [dataflow] further optimize dataflow compile time mlir
#149804 openedJul 21, 2025 bycxy-1993Loading…
[mlir][analysis] Fix a crash in TestMatchReductionPass mlir
#149803 openedJul 21, 2025 byCoTinkerLoading…
[DAG] visitFREEZE - limit freezing of multiple operands backend:AMDGPU backend:NVPTX backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAGSelectionDAGISel as well
#149797 openedJul 21, 2025 byRKSimonLoading…
[AMDGPU][NFC] Run the general bf16 tests for GFX950. backend:AMDGPU
#149796 openedJul 21, 2025 bykosarevLoading…
[SCEV] Don't require NUW at first add when checking A+C1 < (A+C2)<nuw> llvm:analysisIncludes value tracking, cost tables and constant folding
#149795 openedJul 21, 2025 byfhahnLoading…
[LV] Also clamp MaxVF by trip count when maximizing vector bandwidth. llvm:transforms vectorizers
#149794 openedJul 21, 2025 byfhahnLoading…
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