Popular repositoriesLoading

1. avsdpll_1v8avsdpll_1v8Public

   8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room tempe…

   110 41

2. Evaluation-of-NVIDIAs-Camera-to-Robot-Pose-Estimation-Deep-Learning-ResearchEvaluation-of-NVIDIAs-Camera-to-Robot-Pose-Estimation-Deep-Learning-ResearchPublic

   Evaluation of the Single-Image Camera-to-Robot Pose Estimation deep learning research by NVIDIA on the Jaco Gen 2 6DoF KG-3 Robot Arm from Kinova Robotics.

   Python 7

3. caravel_avsdpll1v8caravel_avsdpll1v8Public

   PLL IP on Caravel with OpAmps

   Verilog 4 1

4. Analog-Neural-NetworkAnalog-Neural-NetworkPublic

   Verilog 4

5. avsdpll1v8_caravelavsdpll1v8_caravelPublic

   Forked fromefabless/caravel_mpw-one

   PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC

   Verilog 3

6. rosvinorosvinoPublic

   A ROS package for offloading inference to the Intel Movidius VPU Neural Compute Stick. Also, Evaluation of the Intel Movidius VPU Neural Compute Stick for Real-Time Inference.

   C++ 2 1