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timm bits#804

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rwightman wants to merge101 commits intomain
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timm bits#804

rwightman wants to merge101 commits intomainfrombits_and_tpu

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rwightman
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The branch associated with this PR is for development oftimm bits -- a significant update and reorganizaiton of timm's training scripts and associated modules. It works w/ TPUs (PyTorch XLA) and GPUs (PyTorch) and possibly DeepSpeed.

This PR is still a long ways from being merged. Having the branch as a PR helps w/ visibility of the ongoing work.

Jasha10, dedeswim, alleniver, Dreamer312, ternaus, and Smartappli reacted with thumbs up emojiSmartappli reacted with heart emojiSmartappli reacted with rocket emojinateraw, LaVieEnRoseSMZ, hiyyg, Jasha10, nhannguyen2709, sramroach, and alleniver reacted with eyes emoji
rwightmanand others added30 commitsApril 20, 2021 17:15
…step closure used, metrics base impl w/ distributed reduce, many tweaks/fixes.
…h XLA usage on TPU-VM. Add some FIXMEs and fold train_cfg into train_state by default.
… XLA (pushing into transforms), revamp of transform/preproc config, etc ongoing...
rwightmanand others added29 commitsFebruary 28, 2022 16:33
…ers more similar. Fix workers=0 compatibility. Add ImageNet22k/12k synset defs.
Add support for different TFDS `BuilderConfig`s
Fix issue with `torchvision`'s `ImageNet`
@Smartappli
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is this still in progress ?

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@rwightman@Smartappli@dedeswim

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