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Commit6a128c6

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gbmhunterfpistm
andcommitted
Added NUCLEO_F070RB
Supersedestm32duino#1167Signed-off-by: Geoffrey Hunter <gbmhunter@gmail.com>Co-authored-by: Frederic.Pillon <frederic.pillon@st.com>
1 parentbbadf22 commit6a128c6

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6 files changed

+556
-2
lines changed

6 files changed

+556
-2
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‎README.md

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Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| Status| Device(s)| Name| Release| Notes|
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| :----:| :-------:| ----| :-----:| :----|
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|:green_heart:| STM32F030R8|[Nucleo F030R8](http://www.st.com/en/evaluation-tools/nucleo-f030r8.html)|*0.2.0*||
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|:yellow_heart:| STM32F070RB|[Nucleo F070RB](http://www.st.com/en/evaluation-tools/nucleo-f070rb.html)|**2.0.0**||
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|:green_heart:| STM32F072RB|[Nucleo F072RB](http://www.st.com/en/evaluation-tools/nucleo-f072rb.html)|*1.9.0*||
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|:green_heart:| STM32F091RC|[Nucleo F091RC](http://www.st.com/en/evaluation-tools/nucleo-f091rc.html)|*0.1.0*||
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|:green_heart:| STM32F103RB|[Nucleo F103RB](http://www.st.com/en/evaluation-tools/nucleo-f103rb.html)|*0.2.0*||
@@ -161,6 +162,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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|:yellow_heart:| STM32F042C4<br>STM32F042C6| Generic Board|**2.0.0**||
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|:yellow_heart:| STM32F051K6U<br>STM32F051K8U| Generic Board|**2.0.0**||
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|:yellow_heart:| STM32F070CB| Generic Board|**2.0.0**||
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|:yellow_heart:| STM32F070RB| Generic Board|**2.0.0**||
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|:yellow_heart:| STM32F072C8<br>STM32F072CB| Generic Board|**2.0.0**||
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|:yellow_heart:| STM32F072R8<br>STM32F072RB| Generic Board|**2.0.0**||
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|:yellow_heart:| STM32F091RB<br>STM32F091RC| Generic Board|**2.0.0**||

‎boards.txt

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@@ -208,6 +208,18 @@ Nucleo_64.menu.pnum.NUCLEO_F030R8.build.product_line=STM32F030x8
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Nucleo_64.menu.pnum.NUCLEO_F030R8.build.variant=STM32F0xx/F030R8T
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Nucleo_64.menu.pnum.NUCLEO_F030R8.build.cmsis_lib_gcc=arm_cortexM0l_math
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# NUCLEO_F070RB board
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Nucleo_64.menu.pnum.NUCLEO_F070RB=Nucleo F070RB
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Nucleo_64.menu.pnum.NUCLEO_F070RB.node="NODE_F070RB,NUCLEO"
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Nucleo_64.menu.pnum.NUCLEO_F070RB.upload.maximum_size=131072
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Nucleo_64.menu.pnum.NUCLEO_F070RB.upload.maximum_data_size=16384
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Nucleo_64.menu.pnum.NUCLEO_F070RB.build.mcu=cortex-m0
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Nucleo_64.menu.pnum.NUCLEO_F070RB.build.board=NUCLEO_F070RB
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Nucleo_64.menu.pnum.NUCLEO_F070RB.build.series=STM32F0xx
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Nucleo_64.menu.pnum.NUCLEO_F070RB.build.product_line=STM32F070xB
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Nucleo_64.menu.pnum.NUCLEO_F070RB.build.variant=STM32F0xx/F070RBT
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Nucleo_64.menu.pnum.NUCLEO_F070RB.build.cmsis_lib_gcc=arm_cortexM0l_math
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# NUCLEO_F072RB board
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Nucleo_64.menu.pnum.NUCLEO_F072RB=Nucleo F072RB
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Nucleo_64.menu.pnum.NUCLEO_F072RB.node="NODE_F072RB,NUCLEO"
@@ -963,6 +975,14 @@ GenF0.menu.pnum.GENERIC_F070CBTX.build.board=GENERIC_F070CBTX
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GenF0.menu.pnum.GENERIC_F070CBTX.build.product_line=STM32F070xB
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GenF0.menu.pnum.GENERIC_F070CBTX.build.variant=STM32F0xx/F070CBT
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# Generic F070RBTx
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GenF0.menu.pnum.GENERIC_F070RBTX=Generic F070RBTx
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GenF0.menu.pnum.GENERIC_F070RBTX.upload.maximum_size=131072
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GenF0.menu.pnum.GENERIC_F070RBTX.upload.maximum_data_size=16384
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GenF0.menu.pnum.GENERIC_F070RBTX.build.board=GENERIC_F070RBTX
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GenF0.menu.pnum.GENERIC_F070RBTX.build.product_line=STM32F070xB
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GenF0.menu.pnum.GENERIC_F070RBTX.build.variant=STM32F0xx/F070RBT
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# Generic F072C8Tx
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GenF0.menu.pnum.GENERIC_F072C8TX=Generic F072C8Tx
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GenF0.menu.pnum.GENERIC_F072C8TX.upload.maximum_size=65536

‎variants/STM32F0xx/F070RBT/generic_clock.c

Lines changed: 34 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,40 @@
2020
*/
2121
WEAKvoidSystemClock_Config(void)
2222
{
23-
/* SystemClock_Config can be generated by STM32CubeMX */
24-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
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RCC_OscInitTypeDefRCC_OscInitStruct= {};
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RCC_ClkInitTypeDefRCC_ClkInitStruct= {};
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RCC_PeriphCLKInitTypeDefPeriphClkInit= {};
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType=RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState=RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue=RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState=RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource=RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLMUL=RCC_PLL_MUL6;
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RCC_OscInitStruct.PLL.PREDIV=RCC_PREDIV_DIV1;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct)!=HAL_OK) {
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
41+
*/
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RCC_ClkInitStruct.ClockType=RCC_CLOCKTYPE_HCLK |RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1;
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RCC_ClkInitStruct.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider=RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider=RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct,FLASH_LATENCY_1)!=HAL_OK) {
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection=RCC_PERIPHCLK_USB;
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PeriphClkInit.UsbClockSelection=RCC_USBCLKSOURCE_PLL;
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54+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)!=HAL_OK) {
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Error_Handler();
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}
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}
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#endif/* ARDUINO_GENERIC_* */
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1+
/**
2+
******************************************************************************
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* @file LinkerScript.ld
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* @author Auto-generated by STM32CubeIDE
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* @brief Linker script for STM32F070RBTx Device from STM32F0 series
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* 128Kbytes FLASH
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* 16Kbytes RAM
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*
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* Set heap size, stack size and stack location according
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* to application requirements.
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*
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* Set memory bank area and size if external memory is used
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of theLicense at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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27+
/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack =ORIGIN(RAM) +LENGTH(RAM);/* end of "RAM" Ram type memory */
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_Min_Heap_Size = 0x200;/* required amount of heap */
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_Min_Stack_Size = 0x400;/* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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RAM (xrw) :ORIGIN = 0x20000000,LENGTH = LD_MAX_DATA_SIZE
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FLASH (rx) :ORIGIN = 0x8000000 + LD_FLASH_OFFSET,LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
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}
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/* Sections */
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SECTIONS
45+
{
46+
/* The startup code into "FLASH" Rom type memory */
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.isr_vector :
48+
{
49+
. =ALIGN(4);
50+
KEEP(*(.isr_vector)) /* Startup code */
51+
. =ALIGN(4);
52+
} >FLASH
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/* The program code and other data into "FLASH" Rom type memory */
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.text :
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{
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. =ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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67+
. =ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >FLASH
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/* Constant data into "FLASH" Rom type memory */
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.rodata :
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{
74+
. =ALIGN(4);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. =ALIGN(4);
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} >FLASH
79+
80+
.ARM.extab : {
81+
. =ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
83+
. =ALIGN(4);
84+
} >FLASH
85+
86+
.ARM : {
87+
. =ALIGN(4);
88+
__exidx_start = .;
89+
*(.ARM.exidx*)
90+
__exidx_end = .;
91+
. =ALIGN(4);
92+
} >FLASH
93+
94+
.preinit_array :
95+
{
96+
. =ALIGN(4);
97+
PROVIDE_HIDDEN (__preinit_array_start = .);
98+
KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
100+
. =ALIGN(4);
101+
} >FLASH
102+
103+
.init_array :
104+
{
105+
. =ALIGN(4);
106+
PROVIDE_HIDDEN (__init_array_start = .);
107+
KEEP (*(SORT(.init_array.*)))
108+
KEEP (*(.init_array*))
109+
PROVIDE_HIDDEN (__init_array_end = .);
110+
. =ALIGN(4);
111+
} >FLASH
112+
113+
.fini_array :
114+
{
115+
. =ALIGN(4);
116+
PROVIDE_HIDDEN (__fini_array_start = .);
117+
KEEP (*(SORT(.fini_array.*)))
118+
KEEP (*(.fini_array*))
119+
PROVIDE_HIDDEN (__fini_array_end = .);
120+
. =ALIGN(4);
121+
} >FLASH
122+
123+
/* Used by the startup to initialize data */
124+
_sidata =LOADADDR(.data);
125+
126+
/* Initialized data sections into "RAM" Ram type memory */
127+
.data :
128+
{
129+
. =ALIGN(4);
130+
_sdata = .; /* create a global symbol at data start */
131+
*(.data) /* .data sections */
132+
*(.data*) /* .data* sections */
133+
*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
135+
136+
. =ALIGN(4);
137+
_edata = .; /* define a global symbol at data end */
138+
139+
} >RAM AT> FLASH
140+
141+
/* Uninitialized data section into "RAM" Ram type memory */
142+
. =ALIGN(4);
143+
.bss :
144+
{
145+
/* This is used by the startup in order to initialize the .bss section */
146+
_sbss = .; /* define a global symbol at bss start */
147+
__bss_start__ = _sbss;
148+
*(.bss)
149+
*(.bss*)
150+
*(COMMON)
151+
152+
. =ALIGN(4);
153+
_ebss = .; /* define a global symbol at bss end */
154+
__bss_end__ = _ebss;
155+
} >RAM
156+
157+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
158+
._user_heap_stack :
159+
{
160+
. =ALIGN(8);
161+
PROVIDE ( end = . );
162+
PROVIDE ( _end = . );
163+
. = . + _Min_Heap_Size;
164+
. = . + _Min_Stack_Size;
165+
. =ALIGN(8);
166+
} >RAM
167+
168+
/* Remove information from the compiler libraries */
169+
/DISCARD/ :
170+
{
171+
libc.a ( * )
172+
libm.a ( * )
173+
libgcc.a ( * )
174+
}
175+
176+
.ARM.attributes 0 : { *(.ARM.attributes) }
177+
}

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