@@ -464,14 +464,28 @@ void i2s_set_dividers(uint8_t div1, uint8_t div2) {
464464 div1 &= I2SBDM;
465465 div2 &= I2SCDM;
466466
467+ /*
468+ Following this post: https://github.com/esp8266/Arduino/issues/2590
469+ We should reset the transmitter while changing the configuration bits to avoid random distortion.
470+ */
471+
472+ uint32_t i2sc_temp = I2SC;
473+ i2sc_temp |= (I2STXR);// Hold transmitter in reset
474+ I2SC = i2sc_temp;
475+
467476// trans master(active low), recv master(active_low), !bits mod(==16 bits/chanel), clear clock dividers
468- I2SC &= ~(I2STSM | I2SRSM | (I2SBMM << I2SBM) | (I2SBDM << I2SBD) | (I2SCDM << I2SCD));
477+ i2sc_temp &= ~(I2STSM | I2SRSM | (I2SBMM << I2SBM) | (I2SBDM << I2SBD) | (I2SCDM << I2SCD));
469478
470479// I2SRF = Send/recv right channel first (? may be swapped form I2S spec of WS=0 => left)
471480// I2SMR = MSB recv/xmit first
472481// I2SRMS, I2STMS = 1-bit delay from WS to MSB (I2S format)
473482// div1, div2 = Set I2S WS clock frequency. BCLK seems to be generated from 32x this
474- I2SC |= I2SRF | I2SMR | I2SRMS | I2STMS | (div1 << I2SBD) | (div2 << I2SCD);
483+ i2sc_temp |= I2SRF | I2SMR | I2SRMS | I2STMS | (div1 << I2SBD) | (div2 << I2SCD);
484+
485+ I2SC = i2sc_temp;
486+
487+ i2sc_temp &= ~(I2STXR);// Release reset
488+ I2SC = i2sc_temp;
475489}
476490
477491float i2s_get_real_rate (){