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(This is an 8-bit version, please switch to the corresponding branch for the 32-bit version.)

1. CDBUS Protocol
2. Block Diagram
3. Registers
4. Interface
5. Examples
6. Simulation
7. Ready To Use Devices
8. License

CDBUS is a simple protocol designed for serial ports and serial bus communication, commonly employed in RS-485 buses.It utilizes hardware arbitration and other mechanisms to avoid data conflicts, allowing nodes to freely transmit and receive data packets,thereby overcoming the limitations of single-master polling.

CDBUS has a 3-byte header:[src_addr, dst_addr, data_len], followed by user data, and concluding with a 2-byte CRC (identical to MODBUS CRC).

The CDBUS protocol at the byte level can be directly used for traditional serial communication,such as traditional UART, RS-232, RS-485, and USB virtual serial ports.

The full CDBUS protocol at the bit level requires dedicated hardware controllers (or software emulation)to achieve conflict avoidance, higher speeds, and strong real-time performance.

• It introduces an arbitration mechanism, similar to the CAN bus, to automatically avoid conflicts.
• Supporting dual baud rates achieves high-speed communication,with the maximum baud rate during the high-speed phase up to:sysclk ÷ 3. (e.g. 50 Mbps for 150 MHzsysclk.)
• Supports unicast, multicast and broadcast.
• The maximum user data size is 253 bytes.
• Hardware packing, unpacking, verification and filtering, saving your time and CPU usage.
• Compatible with traditional RS-485 hardware (arbitration function remains effective).

The protocol timing example, consisting of only one byte of user data:
(You can configure the lengths of idle time and transmission permit time.)

Tips:

• When a high-priority node needs to send unimportant data, we can dynamically increase the transmission permit time (TX_PERMIT_LEN).

Arbitration example:

Example waveforms for TX output and TX_EN pins:

The RX data sampling point for reception is at 1/2 bit; for TX readback, it's at 3/4 bit.

In CDBUS-A mode, if the low-speed portion takes longer, it can become a bottleneck for communication efficiency.

To address this, single-rate peer-to-peer bus communication can be achieved using CDBUS-BS mode:

• Different nodes have different configurations for the TX_PERMIT_LEN parameter, requiring sufficiently large differences to avoid conflicts.
• If any node has pending data frames waiting to be sent before the transmission permit point, transmission starts from that point.
• Otherwise, wait until the idle time exceeds MAX_IDLE_LEN. When there are pending data frames waiting for transmission,first send a break character to bring the bus out of the idle state.

The CDBUS-BS mode is suitable for high-speed applications with few nodes, and it is also suitable for software implementation.

SETTING:

TX_PRE_LEN:

Example waveforms for TX output and TX_EN pins (TX_PRE_LEN = 1 bit):

Unused for Arbitration mode and the break character automatically generated by BS mode.

FILTERS:

Match from top to bottom:

For example, addresses from 0xe0 to 0xfe can be reserved for multicast address.

The default value 0xff of FILTER_Mx means not enabled.

DIV_xx_x:

Baud rate divider value:DIV_xx[15:0] = sysclk ÷ baud_rate − 1

The minimum value is 2.

For single rate, DIV_HS needs to be set to the same value as DIV_LS.

INT_FLAG:

Reading this register will automatically clear bit7, bit6, bit4, bit3 and bit2.

INT_MASK:

Output of irq = ((INT_FLAG & INT_MASK) != 0).

RX_CTRL:

TX_CTRL:

RX_PAGE_FLAG:

A value of zero indicates that the frame in the current RX page is correct;
Non-zero indicates the pointer to the last received byte of the disrupted frame, including CRC.

Always zero ifsave broken frame is not enabled.

parameter DIV_LS=346,// default: 115200 bps for 40MHz clkparameter DIV_HS=346input           clk,// core clockinput           reset_n,// async active-low resetinput           chip_select,output          irq,// interrupt output// avalon-mm slave interface, read and write without latency// support burst read and write (normally for REG_TX and REG_RX)input   [4:0]   csr_address,input           csr_read,output  [7:0]   csr_readdata,input           csr_write,input   [7:0]   csr_writedata,// connect to external PHY chip, e.g. MAX3485input           rx,output          tx,output          tx_en

# Configurationwrite(REG_SETTING, [0x11])# Enable push-pull output# TXwrite(REG_TX, [0x0c,0x0d,0x01,0xcd])# Write frame without CRCwhile (read(REG_INT_FLAG)&0x20)==0:# Make sure we can successfully switch to the next pagepasswrite(REG_TX_CTRL, [0x03])# Trigger sending by switching TX page# RXwhile (read(REG_INT_FLAG)&0x02)==0:# Wait for RX page readypassheader=read(REG_RX,len=3)data=read(REG_RX,len=header[2])write(REG_RX_CTRL, [0x03])# Release RX page

Installiverilog (>= v10) andcocotb, gototests/ folder, run./test_all.sh or./test_all.sh test_xxx.py.(You can checkout the waveformcdbus.vcd by GTKWave.)

The CDCTL controllers family incorporates the CDBUS IP Core, providing peripheral interfaces such as SPI, I²C, and PCIe.
E.g. The tiny CDCTL-Bx module supports SPI and I²C interfaces:
(The source code and gerber files for this module are fully open-source and located in theexample/ directory.)

For a list of CDBUS-related ASIC chips, please refer to thewiki page.

More relevant projects that may interest you:

• CDBUS GUI:https://github.com/dukelec/cdbus_gui
• CDNET:https://github.com/dukelec/cdnet

This Source Code Form is subject to the terms of the MozillaPublic License, v. 2.0. If a copy of the MPL was not distributedwith this file, You can obtain one at https://mozilla.org/MPL/2.0/.Notice: The scope granted to MPL excludes the ASIC industry.The CDBUS protocol is royalty-free for everyone except chip manufacturers.Copyright (c) 2017 DUKELEC, All rights reserved.