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Optimize Vector128<long> multiplication for arm64#104177

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Merged
EgorBo merged 8 commits intodotnet:mainfromEgorBo:mul-long-arm64
Jul 2, 2024

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Follow up to#103555 for arm64

@ghostghost added the area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI labelJun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}
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Tagging subscribers to this area:@JulieLeeMSFT,@jakobbotsch
See info inarea-owners.md if you want to be subscribed.

Comment on lines 21932 to 21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)Unknown processor  Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD  Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs:Main vsPR 🔥
Hot asm:Main vsPR
Hot functions:Main vsPR

For cleanperf results, make sure you have just one[Benchmark] in your app.

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neon-sunset commentedJul 1, 2024
edited
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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores,UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment on lines 22005 to 22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
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nit: UsegtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBoEgorBo marked this pull request as ready for reviewJuly 2, 2024 18:03
@EgorBoEgorBo merged commit6e039a8 intodotnet:mainJul 2, 2024
@EgorBoEgorBo deleted the mul-long-arm64 branchJuly 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);
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Why bitcast instead ofToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from theToScalar path

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@EgorBoEgorBoJul 2, 2024
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@tannergooding because op2 can be either 8-byteTYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for bothMUL(vector, vector) andMUL(vector, scalar) (wherescalar is broadcasted)

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Ah, that makes sense, 👍

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