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Accelerate Vector128<long>::op_Multiply on x64#103555

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Merged
EgorBo merged 21 commits intodotnet:mainfromEgorBo:arm-mul-64bit
Jun 28, 2024
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ae17211
Accelerate Vector128 mul for long/ulong
EgorBoJun 17, 2024
afda312
better ulong version
EgorBoJun 17, 2024
ab01574
fix build
EgorBoJun 17, 2024
21b42de
Update Vector128_1.cs
EgorBoJun 17, 2024
581f1e2
Sse41 version
EgorBoJun 17, 2024
49a359f
Update src/libraries/System.Private.CoreLib/src/System/Runtime/Intrin…
EgorBoJun 17, 2024
57898f0
Update Vector128_1.cs
EgorBoJun 17, 2024
f1be705
Update Vector128_1.cs
EgorBoJun 19, 2024
95d0eb8
Update Vector128_1.cs
EgorBoJun 19, 2024
dcfd93d
Update Vector128_1.cs
EgorBoJun 19, 2024
7fec9e3
Update Vector128_1.cs
EgorBoJun 19, 2024
e172296
Update Vector128_1.cs
EgorBoJun 19, 2024
0456d12
Update Vector128_1.cs
EgorBoJun 20, 2024
8af6104
Merge branch 'main' of https://github.com/dotnet/runtime into arm-mul…
EgorBoJun 20, 2024
69572a2
Update Vector128_1.cs
EgorBoJun 20, 2024
d607549
clean up
EgorBoJun 20, 2024
573a37b
move to jit
EgorBoJun 20, 2024
3790d1b
clean up
EgorBoJun 20, 2024
60441f3
revert unrelated changes
EgorBoJun 21, 2024
5b78ddd
Merge branch 'main' of https://github.com/dotnet/runtime into arm-mul…
EgorBoJun 28, 2024
cc257dd
Address feedback
EgorBoJun 28, 2024
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clean up
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@EgorBo
EgorBo committedJun 20, 2024
commitd60754954319ad596fec2a69875ecc7316bfc6cd
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Original file line numberDiff line numberDiff line change
Expand Up@@ -263,30 +263,31 @@ public static Vector128<T> Zero
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static Vector128<T> operator *(Vector128<T> left, Vector128<T> right)
{
// TODO: move this to JIT
if (Sse41.IsSupported && (typeof(T) == typeof(long) || typeof(T) == typeof(ulong)))
// Multiplication for long/ulong is currently accelerated only with AVX512
// We need workarounds for ARM64 and pre-AVX512 hw:
// TODO: move this expansion to JIT
if (typeof(T) == typeof(long) || typeof(T) == typeof(ulong))
{
Vector128<ulong> a = left.AsUInt64();
Vector128<ulong> b = right.AsUInt64();
return Unsafe.BitCast<Vector128<ulong>, Vector128<T>>(
Sse2.Add(
Sse2.Multiply(a.AsUInt32(), b.AsUInt32()).AsUInt64(),
Sse2.Shuffle(
Ssse3.HorizontalAdd(
Sse41.MultiplyLow(a.AsUInt32(),
Sse2.Shuffle(b.AsUInt32(), 0xB1)).AsInt32(), Vector128<int>.Zero), 0x73).AsUInt64()));
}
if (AdvSimd.Arm64.IsSupported && (typeof(T) == typeof(long) || typeof(T) == typeof(ulong)))
{
Vector128<ulong> a = left.AsUInt64();
Vector128<ulong> b = right.AsUInt64();
Vector64<uint> aHi = AdvSimd.ShiftRightLogicalNarrowingLower(a.AsUInt64(), 32);
Vector64<uint> aLo = AdvSimd.ExtractNarrowingLower(a.AsUInt64());
Vector64<uint> bHi = AdvSimd.ShiftRightLogicalNarrowingLower(b.AsUInt64(), 32);
Vector64<uint> bLo = AdvSimd.ExtractNarrowingLower(b.AsUInt64());
Vector128<ulong> ret64 = AdvSimd.MultiplyWideningLower(aHi, bLo);
ret64 = AdvSimd.MultiplyWideningLowerAndAdd(ret64, aLo, bHi);
return AdvSimd.MultiplyWideningLowerAndAdd(ret64 << 32, aLo, bLo).As<ulong, T>();
if (Sse41.IsSupported)
{
Vector128<uint> tmp1 = Sse2.Shuffle(right.AsUInt32(), 0xB1); // _MM_SHUFFLE(2,3,0,1)
Vector128<uint> tmp2 = Sse41.MultiplyLow(left.AsUInt32(), tmp1);
Vector128<int> tmp3 = Ssse3.HorizontalAdd(tmp2.AsInt32(), Vector128<int>.Zero);
Vector128<int> tmp4 = Sse2.Shuffle(tmp3, 0x73); // _MM_SHUFFLE(1,3,0,3)
Vector128<ulong> tmp5 = Sse2.Multiply(left.AsUInt32(), right.AsUInt32());
return Unsafe.BitCast<Vector128<ulong>, Vector128<T>>(tmp5.AsUInt64() + tmp4.AsUInt64());
}
if (AdvSimd.Arm64.IsSupported)
{
Vector64<uint> lHi = AdvSimd.ShiftRightLogicalNarrowingLower(left.AsUInt64(), 32);
Vector64<uint> lLo = AdvSimd.ExtractNarrowingLower(left.AsUInt64());
Vector64<uint> rHi = AdvSimd.ShiftRightLogicalNarrowingLower(right.AsUInt64(), 32);
Vector64<uint> rLo = AdvSimd.ExtractNarrowingLower(right.AsUInt64());
Vector128<ulong> ret64 = AdvSimd.MultiplyWideningLower(lHi, rLo);
ret64 = AdvSimd.MultiplyWideningLowerAndAdd(ret64, lLo, rHi);
return Unsafe.BitCast<Vector128<ulong>, Vector128<T>>(
AdvSimd.MultiplyWideningLowerAndAdd(ret64 << 32, lLo, rLo));
}
}

return Vector128.Create(
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