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SystemVerilog parser library fully compliant with IEEE 1800-2017
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dalance/sv-parser
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SystemVerilog parser library fully compliant withIEEE 1800-2017.
- morty: A SystemVerilog source file pickler
- svinst: Determines the modules declared and instantiated in a SystemVerilog file
- svlint: SystemVerilog linter
- svls: SystemVerilog language server
[dependencies]sv-parser ="0.13.3"
sv-parser providesparse_sv
function which returnsSyntaxTree
.SyntaxTree
shows Concrete Syntax Tree. It has the preprocessed string and the parsed tree.
RefNode
shows a reference to any node ofSyntaxTree
.You can getRefNode
through an iterator ofSyntaxTree
.Variant names ofRefNode
follows "Annex A Formal syntax" of IEEE 1800-2017.
Locate
shows a position of token. All leaf node ofSyntaxTree
isLocate
.You can get string fromLocate
byget_str
.
The following example parses a SystemVerilog source file and shows module names.
use std::collections::HashMap;use std::env;use std::path::PathBuf;use sv_parser::{parse_sv, unwrap_node,Locate,RefNode};fnmain(){let args:Vec<String> = env::args().collect();// The path of SystemVerilog source filelet path =PathBuf::from(&args[1]);// The list of defined macroslet defines =HashMap::new();// The list of include pathslet includes:Vec<PathBuf> =Vec::new();// Parselet result =parse_sv(&path,&defines,&includes,false,false);ifletOk((syntax_tree, _)) = result{// &SyntaxTree is iterablefor nodein&syntax_tree{// The type of each node is RefNodematch node{RefNode::ModuleDeclarationNonansi(x) =>{// unwrap_node! gets the nearest ModuleIdentifier from xlet id =unwrap_node!(x,ModuleIdentifier).unwrap();let id =get_identifier(id).unwrap();// Original string can be got by SyntaxTree::get_str(self, locate: &Locate)let id = syntax_tree.get_str(&id).unwrap();println!("module: {}", id);}RefNode::ModuleDeclarationAnsi(x) =>{let id =unwrap_node!(x,ModuleIdentifier).unwrap();let id =get_identifier(id).unwrap();let id = syntax_tree.get_str(&id).unwrap();println!("module: {}", id);} _ =>(),}}}else{println!("Parse failed");}}fnget_identifier(node:RefNode) ->Option<Locate>{// unwrap_node! can take multiple typesmatchunwrap_node!(node,SimpleIdentifier,EscapedIdentifier){Some(RefNode::SimpleIdentifier(x)) =>{returnSome(x.nodes.0);}Some(RefNode::EscapedIdentifier(x)) =>{returnSome(x.nodes.0);} _ =>None,}}
Licensed under either of
- Apache License, Version 2.0, (LICENSE-APACHE orhttp://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT orhttp://opensource.org/licenses/MIT)
at your option.
Unless you explicitly state otherwise, any contribution intentionallysubmitted for inclusion in the work by you, as defined in the Apache-2.0license, shall be dual licensed as above, without any additional terms orconditions.
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SystemVerilog parser library fully compliant with IEEE 1800-2017
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