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libnvdimm, nfit: fix persistence domain reporting
The persistence domain is a point in the platform where once writesreach that destination the platform claims it will make them persistentrelative to power loss. In the ACPI NFIT this is currently communicatedas 2 bits in the "NFIT - Platform Capabilities Structure". The bitscomprise a hierarchy, i.e. bit0 "CPU Cache Flush to NVDIMM Durability onPower Loss Capable" implies bit1 "Memory Controller Flush to NVDIMMDurability on Power Loss Capable".Commit96c3a23 "libnvdimm: expose platform persistence attr..."shows the persistence domain as flags, but it's really an enumeratedhierarchy.Fix this newly introduced user ABI to show the closest availablepersistence domain before userspace develops dependencies on seeing, orneeding to develop code to tolerate, the raw NFIT flags communicatedthrough the libnvdimm-generic region attribute.Fixes:96c3a23 ("libnvdimm: expose platform persistence attr...")Reviewed-by: Dave Jiang <dave.jiang@intel.com>Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>Cc: Ross Zwisler <ross.zwisler@linux.intel.com>Signed-off-by: Dan Williams <dan.j.williams@intel.com>1 parent896196d commitfe9a552
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