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forked fromtorvalds/linux

Commite64b956

Browse files
committed
Merge branch 'x86/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Thomas Gleixner: "A small set of fixes for x86: - Add missing instruction suffixes to assembly code so it can be compiled by newer GAS versions without warnings. - Switch refcount WARN exceptions to UD2 as we did in general - Make the reboot on Intel Edison platforms work - A small documentation update so text and sample command match"* 'x86/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Documentation, x86, resctrl: Make text and sample command match x86/platform/intel-mid: Handle Intel Edison reboot correctly x86/asm: Add instruction suffixes to bitops x86/entry/64: Add instruction suffix x86/refcounts: Switch to UD2 for exceptions
2 parents7225a44 +3000974 commite64b956

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6 files changed

+21
-18
lines changed

6 files changed

+21
-18
lines changed

‎Documentation/x86/intel_rdt_ui.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -671,7 +671,7 @@ occupancy of the real time threads on these cores.
671671
# mkdir p1
672672

673673
Move the cpus 4-7 over to p1
674-
# echo f0 >p0/cpus
674+
# echo f0 >p1/cpus
675675

676676
View the llc occupancy snapshot
677677

‎arch/x86/entry/entry_64.S‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ END(native_usergs_sysret64)
5555

5656
.macro TRACE_IRQS_FLAGSflags:req
5757
#ifdef CONFIG_TRACE_IRQFLAGS
58-
bt$9, \flags/* interrupts off? */
58+
btl$9, \flags/* interrupts off? */
5959
jnc1f
6060
TRACE_IRQS_ON
6161
1:

‎arch/x86/include/asm/bitops.h‎

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ set_bit(long nr, volatile unsigned long *addr)
7878
:"iq" ((u8)CONST_MASK(nr))
7979
:"memory");
8080
}else {
81-
asmvolatile(LOCK_PREFIX"bts %1,%0"
81+
asmvolatile(LOCK_PREFIX__ASM_SIZE(bts)" %1,%0"
8282
:BITOP_ADDR(addr) : "Ir" (nr) : "memory");
8383
}
8484
}
@@ -94,7 +94,7 @@ set_bit(long nr, volatile unsigned long *addr)
9494
*/
9595
static__always_inlinevoid__set_bit(longnr,volatileunsigned long*addr)
9696
{
97-
asmvolatile("bts %1,%0" :ADDR :"Ir" (nr) :"memory");
97+
asmvolatile(__ASM_SIZE(bts)" %1,%0" :ADDR :"Ir" (nr) :"memory");
9898
}
9999

100100
/**
@@ -115,7 +115,7 @@ clear_bit(long nr, volatile unsigned long *addr)
115115
:CONST_MASK_ADDR(nr,addr)
116116
:"iq" ((u8)~CONST_MASK(nr)));
117117
}else {
118-
asmvolatile(LOCK_PREFIX"btr %1,%0"
118+
asmvolatile(LOCK_PREFIX__ASM_SIZE(btr)" %1,%0"
119119
:BITOP_ADDR(addr)
120120
:"Ir" (nr));
121121
}
@@ -137,7 +137,7 @@ static __always_inline void clear_bit_unlock(long nr, volatile unsigned long *ad
137137

138138
static__always_inlinevoid__clear_bit(longnr,volatileunsigned long*addr)
139139
{
140-
asmvolatile("btr %1,%0" :ADDR :"Ir" (nr));
140+
asmvolatile(__ASM_SIZE(btr)" %1,%0" :ADDR :"Ir" (nr));
141141
}
142142

143143
static__always_inlineboolclear_bit_unlock_is_negative_byte(longnr,volatileunsigned long*addr)
@@ -182,7 +182,7 @@ static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *
182182
*/
183183
static__always_inlinevoid__change_bit(longnr,volatileunsigned long*addr)
184184
{
185-
asmvolatile("btc %1,%0" :ADDR :"Ir" (nr));
185+
asmvolatile(__ASM_SIZE(btc)" %1,%0" :ADDR :"Ir" (nr));
186186
}
187187

188188
/**
@@ -201,7 +201,7 @@ static __always_inline void change_bit(long nr, volatile unsigned long *addr)
201201
:CONST_MASK_ADDR(nr,addr)
202202
:"iq" ((u8)CONST_MASK(nr)));
203203
}else {
204-
asmvolatile(LOCK_PREFIX"btc %1,%0"
204+
asmvolatile(LOCK_PREFIX__ASM_SIZE(btc)" %1,%0"
205205
:BITOP_ADDR(addr)
206206
:"Ir" (nr));
207207
}
@@ -217,7 +217,8 @@ static __always_inline void change_bit(long nr, volatile unsigned long *addr)
217217
*/
218218
static__always_inlinebooltest_and_set_bit(longnr,volatileunsigned long*addr)
219219
{
220-
GEN_BINARY_RMWcc(LOCK_PREFIX"bts",*addr,"Ir",nr,"%0",c);
220+
GEN_BINARY_RMWcc(LOCK_PREFIX__ASM_SIZE(bts),
221+
*addr, "Ir", nr, "%0", c);
221222
}
222223

223224
/**
@@ -246,7 +247,7 @@ static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *
246247
{
247248
boololdbit;
248249

249-
asm("bts %2,%1"
250+
asm(__ASM_SIZE(bts)" %2,%1"
250251
CC_SET(c)
251252
:CC_OUT(c) (oldbit),ADDR
252253
:"Ir" (nr));
@@ -263,7 +264,8 @@ static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *
263264
*/
264265
static__always_inlinebooltest_and_clear_bit(longnr,volatileunsigned long*addr)
265266
{
266-
GEN_BINARY_RMWcc(LOCK_PREFIX"btr",*addr,"Ir",nr,"%0",c);
267+
GEN_BINARY_RMWcc(LOCK_PREFIX__ASM_SIZE(btr),
268+
*addr, "Ir", nr, "%0", c);
267269
}
268270

269271
/**
@@ -286,7 +288,7 @@ static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long
286288
{
287289
boololdbit;
288290

289-
asmvolatile("btr %2,%1"
291+
asmvolatile(__ASM_SIZE(btr)" %2,%1"
290292
CC_SET(c)
291293
:CC_OUT(c) (oldbit),ADDR
292294
:"Ir" (nr));
@@ -298,7 +300,7 @@ static __always_inline bool __test_and_change_bit(long nr, volatile unsigned lon
298300
{
299301
boololdbit;
300302

301-
asmvolatile("btc %2,%1"
303+
asmvolatile(__ASM_SIZE(btc)" %2,%1"
302304
CC_SET(c)
303305
:CC_OUT(c) (oldbit),ADDR
304306
:"Ir" (nr) :"memory");
@@ -316,7 +318,8 @@ static __always_inline bool __test_and_change_bit(long nr, volatile unsigned lon
316318
*/
317319
static__always_inlinebooltest_and_change_bit(longnr,volatileunsigned long*addr)
318320
{
319-
GEN_BINARY_RMWcc(LOCK_PREFIX"btc",*addr,"Ir",nr,"%0",c);
321+
GEN_BINARY_RMWcc(LOCK_PREFIX__ASM_SIZE(btc),
322+
*addr, "Ir", nr, "%0", c);
320323
}
321324

322325
static__always_inlineboolconstant_test_bit(longnr,constvolatileunsigned long*addr)
@@ -329,7 +332,7 @@ static __always_inline bool variable_test_bit(long nr, volatile const unsigned l
329332
{
330333
boololdbit;
331334

332-
asmvolatile("bt %2,%1"
335+
asmvolatile(__ASM_SIZE(bt)" %2,%1"
333336
CC_SET(c)
334337
:CC_OUT(c) (oldbit)
335338
:"m" (*(unsigned long*)addr),"Ir" (nr));

‎arch/x86/include/asm/percpu.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -526,7 +526,7 @@ static inline bool x86_this_cpu_variable_test_bit(int nr,
526526
{
527527
boololdbit;
528528

529-
asmvolatile("bt "__percpu_arg(2)",%1"
529+
asmvolatile("btl "__percpu_arg(2)",%1"
530530
CC_SET(c)
531531
:CC_OUT(c) (oldbit)
532532
:"m" (*(unsigned long__percpu*)addr),"Ir" (nr));

‎arch/x86/include/asm/refcount.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
#define_REFCOUNT_EXCEPTION\
1818
".pushsection .text..refcount\n"\
1919
"111:\tlea %[counter], %%" _ASM_CX "\n"\
20-
"112:\t"ASM_UD0 "\n"\
20+
"112:\t"ASM_UD2 "\n"\
2121
ASM_UNREACHABLE\
2222
".popsection\n"\
2323
"113:\n"\

‎arch/x86/platform/intel-mid/intel-mid.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ static void intel_mid_power_off(void)
7979

8080
staticvoidintel_mid_reboot(void)
8181
{
82-
intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT,0);
82+
intel_scu_ipc_simple_command(IPCMSG_COLD_RESET,0);
8383
}
8484

8585
staticunsigned long__initintel_mid_calibrate_tsc(void)

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