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forked fromtorvalds/linux

Commit3b358cd

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drm/i915: Kill the remaining CHV HBR2 leftovers
AFAIK CHV was supposed to have HBR2 originally, but in the end the featurewas dropped. We still have some code leftovers from those early days.Eliminate them.The extra bit for the training pattern seems to be dead in the hardware.I can set it (in fact I can set almost any reserved bit in theregisters) but it doesn't seem to interfere with the operation of thehardware. Either that or I'm very lucky that my displays complete linktraining with the incorrect pattern being sent out.Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>Link:https://patchwork.freedesktop.org/patch/msgid/20180302095656.19662-1-ville.syrjala@linux.intel.comReviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
1 parente400671 commit3b358cd

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2 files changed

+4
-18
lines changed

2 files changed

+4
-18
lines changed

‎drivers/gpu/drm/i915/i915_reg.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4943,8 +4943,6 @@ enum {
49434943
#defineDP_LINK_TRAIN_OFF(3 << 28)
49444944
#defineDP_LINK_TRAIN_MASK(3 << 28)
49454945
#defineDP_LINK_TRAIN_SHIFT28
4946-
#defineDP_LINK_TRAIN_PAT_3_CHV(1 << 14)
4947-
#defineDP_LINK_TRAIN_MASK_CHV((3 << 28)|(1<<14))
49484946

49494947
/* CPT Link training mode */
49504948
#defineDP_LINK_TRAIN_PAT_1_CPT(0 << 8)

‎drivers/gpu/drm/i915/intel_dp.c‎

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -91,8 +91,6 @@ static const struct dp_link_dpll chv_dpll[] = {
9191
{ .p1=4, .p2=2, .n=1, .m1=2, .m2=0x819999a } },
9292
{270000,/* m2_int = 27, m2_fraction = 0 */
9393
{ .p1=4, .p2=1, .n=1, .m1=2, .m2=0x6c00000 } },
94-
{540000,/* m2_int = 27, m2_fraction = 0 */
95-
{ .p1=2, .p2=1, .n=1, .m1=2, .m2=0x6c00000 } }
9694
};
9795

9896
/**
@@ -2900,10 +2898,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
29002898
}
29012899

29022900
}else {
2903-
if (IS_CHERRYVIEW(dev_priv))
2904-
*DP &= ~DP_LINK_TRAIN_MASK_CHV;
2905-
else
2906-
*DP &= ~DP_LINK_TRAIN_MASK;
2901+
*DP &= ~DP_LINK_TRAIN_MASK;
29072902

29082903
switch (dp_train_pat&DP_TRAINING_PATTERN_MASK) {
29092904
caseDP_TRAINING_PATTERN_DISABLE:
@@ -2916,12 +2911,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
29162911
*DP |=DP_LINK_TRAIN_PAT_2;
29172912
break;
29182913
caseDP_TRAINING_PATTERN_3:
2919-
if (IS_CHERRYVIEW(dev_priv)) {
2920-
*DP |=DP_LINK_TRAIN_PAT_3_CHV;
2921-
}else {
2922-
DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2923-
*DP |=DP_LINK_TRAIN_PAT_2;
2924-
}
2914+
DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2915+
*DP |=DP_LINK_TRAIN_PAT_2;
29252916
break;
29262917
}
29272918
}
@@ -3660,10 +3651,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
36603651
DP &= ~DP_LINK_TRAIN_MASK_CPT;
36613652
DP |=DP_LINK_TRAIN_PAT_IDLE_CPT;
36623653
}else {
3663-
if (IS_CHERRYVIEW(dev_priv))
3664-
DP &= ~DP_LINK_TRAIN_MASK_CHV;
3665-
else
3666-
DP &= ~DP_LINK_TRAIN_MASK;
3654+
DP &= ~DP_LINK_TRAIN_MASK;
36673655
DP |=DP_LINK_TRAIN_PAT_IDLE;
36683656
}
36693657
I915_WRITE(intel_dp->output_reg,DP);

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