@@ -22,24 +22,11 @@ VideoCoreIV first stage bootloader.
2222
2323uint32_t g_CPUID ;
2424
25- #define UART_DR (UART_BASE+0x00)
26- #define UART_RSRECR (UART_BASE+0x04)
27- #define UART_FR (UART_BASE+0x18)
28- #define UART_ILPR (UART_BASE+0x20)
2925#define UART_IBRD (UART_BASE+0x24)
3026#define UART_FBRD (UART_BASE+0x28)
3127#define UART_LCRH (UART_BASE+0x2C)
3228#define UART_CR (UART_BASE+0x30)
33- #define UART_IFLS (UART_BASE+0x34)
34- #define UART_IMSC (UART_BASE+0x38)
35- #define UART_RIS (UART_BASE+0x3C)
36- #define UART_MIS (UART_BASE+0x40)
3729#define UART_ICR (UART_BASE+0x44)
38- #define UART_DMACR (UART_BASE+0x48)
39- #define UART_ITCR (UART_BASE+0x80)
40- #define UART_ITIP (UART_BASE+0x84)
41- #define UART_ITOP (UART_BASE+0x88)
42- #define UART_TDR (UART_BASE+0x8C)
4330
4431void uart_putc (unsignedint ch ) {
4532while (UART_MSR & 0x20 );
@@ -72,39 +59,6 @@ void uart_init(void) {
7259mmio_write32 (UART_CR ,0x301 );
7360}
7461
75- void led_init (void ) {
76- unsignedint ra ;
77-
78- ra = GP_FSEL1 ;
79- ra &= ~(7 <<18 );
80- ra |=1 <<18 ;
81-
82- GP_FSEL1 = ra ;
83- }
84-
85- /*
86- #define CM_PLLC_DIGRST_BITS 9:9
87- #define CM_PLLC_DIGRST_SET 0x00000200
88- #define CM_PLLC_ANARST_BITS 8:8
89- #define CM_PLLC_ANARST_SET 0x00000100
90- #define CM_PLLC_HOLDPER_BITS 7:7
91- #define CM_PLLC_HOLDPER_SET 0x00000080
92- #define CM_PLLC_LOADPER_BITS 6:6
93- #define CM_PLLC_LOADPER_SET 0x00000040
94- #define CM_PLLC_HOLDCORE2_BITS 5:5
95- #define CM_PLLC_HOLDCORE2_SET 0x00000020
96- #define CM_PLLC_LOADCORE2_BITS 4:4
97- #define CM_PLLC_LOADCORE2_SET 0x00000010
98- #define CM_PLLC_HOLDCORE1_BITS 3:3
99- #define CM_PLLC_HOLDCORE1_SET 0x00000008
100- #define CM_PLLC_LOADCORE1_BITS 2:2
101- #define CM_PLLC_LOADCORE1_SET 0x00000004
102- #define CM_PLLC_HOLDCORE0_BITS 1:1
103- #define CM_PLLC_HOLDCORE0_SET 0x00000002
104- #define CM_PLLC_LOADCORE0_BITS 0:0
105- #define CM_PLLC_LOADCORE0_SET 0x00000001
106- */
107-
10862void switch_vpu_to_pllc () {
10963A2W_XOSC_CTRL |=A2W_PASSWORD |A2W_XOSC_CTRL_PLLCEN_SET ;
11064
@@ -164,19 +118,13 @@ void set_interrupt(int intno, bool enable) {
164118
165119uint32_t v = mmio_read32 (IC0_BASE + offset )& ~slot ;
166120mmio_write32 (IC0_BASE + offset ,enable ?v |slot :v );
167-
168- printf ("%d: %X\n" ,intno ,mmio_read32 (IC0_BASE + offset ));
169121}
170122
171123extern void sdram_init ();
172124extern void arm_init ();
173125extern void monitor_start ();
174126extern void PEStartPlatform ();
175127
176- void print_crap () {
177- printf ("TB_BOOT_OPT = 0x%X\n" ,TB_BOOT_OPT );
178- }
179-
180128int _main (unsignedint cpuid ,unsignedint load_address ) {
181129switch_vpu_to_pllc ();
182130
@@ -201,11 +149,6 @@ int _main(unsigned int cpuid, unsigned int load_address) {
201149"OPENSOURCE"
202150);
203151
204- printf ("CPUID = 0x%X\n" ,cpuid );
205- printf ("LoadAddr = 0x%X\n" ,load_address );
206-
207- print_crap ();
208-
209152g_CPUID = cpuid ;
210153
211154__cxx_init ();
@@ -221,4 +164,3 @@ int _main(unsigned int cpuid, unsigned int load_address) {
221164
222165panic ("main exiting!" );
223166}
224-