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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open sourceProjects, which areWorkgroups.

Popular repositoriesLoading

chiselchiselPublic
Chisel: A Modern Hardware Design Language
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rocket-chiprocket-chipPublic
Rocket Chip Generator
Scala 3.6k 1.2k
veribleveriblePublic
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
C++ 1.6k 255
riscv-dvriscv-dvPublic
Random instruction generator for RISC-V processor verification
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Cores-VeeR-EH1Cores-VeeR-EH1Public
VeeR EH1 core
SystemVerilog 900 233
firrtlfirrtlPublic archive
Flexible Intermediate Representation for RTL
Scala 747 179

Showing 10 of 112 repositories

caliptra-ss Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
chipsalliance/caliptra-ss’s past year of commit activity
SystemVerilog 30Apache-2.0 30 47 7 UpdatedOct 13, 2025
caliptra-rtl Public
HW Design Collateral for Caliptra RoT IP
chipsalliance/caliptra-rtl’s past year of commit activity
SystemVerilog 112Apache-2.0 63 82 17 UpdatedOct 13, 2025
verilator Public Forked fromverilator/verilator
Verilator open-source SystemVerilog simulator and lint system
chipsalliance/verilator’s past year of commit activity
C++ 41LGPL-3.0 716 0 0 UpdatedOct 13, 2025
t1 Public
chipsalliance/t1’s past year of commit activity
Scala 290Apache-2.0 40 18 25 UpdatedOct 13, 2025
caliptra-sw Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
chipsalliance/caliptra-sw’s past year of commit activity
Rust 127Apache-2.0 68 190 72 UpdatedOct 13, 2025
i3c-core Public
chipsalliance/i3c-core’s past year of commit activity
SystemVerilog 36Apache-2.0 12 12 0 UpdatedOct 13, 2025
caliptra-mcu-sw Public
Caliptra MCU Software
chipsalliance/caliptra-mcu-sw’s past year of commit activity
Rust 21Apache-2.0 23 53 15 UpdatedOct 11, 2025
chips-alliance-website Public
chipsalliance/chips-alliance-website’s past year of commit activity
SCSS 4MIT 7 8 8 UpdatedOct 11, 2025
Caliptra Public
Caliptra IP and firmware for integrated Root of Trust block
chipsalliance/Caliptra’s past year of commit activity
337Apache-2.0 52 58 5 UpdatedOct 11, 2025
sv-tests Public
Test suite designed to check compliance with the SystemVerilog standard.
chipsalliance/sv-tests’s past year of commit activity
SystemVerilog 344ISC 83 47 (5 issues need help) 22 UpdatedOct 11, 2025