It's also worth noting that this is the case forLATCHLO andLATCHHI, too (this was also mentioned briefly in#3).

For the latches, it's less noticeable since their bodies only containdefcell variables, and so there are no non-cell production rules that need to be generated. Although, it does mean that the delay of the latch is affected by the placement of the various internal components.

For the clock buffers, there are no nested cells, so the following production-rule-based cells are created and (assuming I understand correctly) can be placed apart from each other:

• _0_0cell_0_0g0n1na_01ax0
• _0_0cell_0_0g0n_0x0
• _0_0cell_0_0g0n_0x1

Here is an exceprt from acells.act created byprs2cells -Tsky130l:

namespace cell {export defcell g0n1na_01ax0 (bool? in[2]; bool! out){   prs * {   in[0]<10> & in[1]<10> -> out-   ~in[0]<12> & ~in[1]<12> -> out+   }}export defcell g0n_0x0 (bool? in[1]; bool! out){   prs * {   in[0]<5> -> out-   ~in[0]<6> -> out+   }}