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188 | 188 | #defineEHCI_SPLITISOTD 0x00000004/* split transaction isochronous TD */ |
189 | 189 | #defineEHCI_FRAMESPAN 0x00000006/* frame span traversal node */ |
190 | 190 |
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| 191 | +/* Isochronous Transfer Descriptor definitions */ |
| 192 | + |
| 193 | +#defineEITF_STATUS_ACTIVE (1UL<<31) |
| 194 | +#defineEITF_STATUS_DBE (1UL<<30) |
| 195 | +#defineEITF_STATUS_BABBLE (1UL<<29) |
| 196 | +#defineEITF_STATUS_XACTERR (1UL<<28) |
| 197 | +#defineEITF_LENGTH_MASK 0x0fff |
| 198 | +#defineEITF_LENGTH_SHIFT 0 |
| 199 | +#defineEITF_IOC (1UL<<15) |
| 200 | +#defineEITF_PAGESELECT_SHIFT 12 |
| 201 | + |
| 202 | +#defineEITM_BUFFER_BASE 0xfffff000 |
| 203 | +#defineEITM_BUFFER_OFFSET 0x00000fff |
| 204 | +#defineEITM_DEVADDR(x) ((x) & 0x7f) |
| 205 | +#defineEITM_ENDPT(x) (((x) & 0x0f) << 8) |
| 206 | +#defineEITM_MAXPKTSIZE(x) (((x) & 0x07ff) << 0) |
| 207 | +#defineEITM_DIRECTION_IN (1UL<<11) |
| 208 | +#defineEITM_BUFFER_DIR(x) ((x) ? EITM_DIRECTION_IN : 0) |
| 209 | +#defineEITM_SMASK 0x000000ff |
| 210 | +#defineEITM_CMASK 0x0000ff00 |
| 211 | + |
| 212 | +#defineESIM_DEVADDR(x) ((x) & 0x7f) |
| 213 | +#defineESIM_ENDPT(x) (((x) & 0x0f) << 8) |
| 214 | +#defineESIM_DIRECTION_IN (1UL<<11) |
| 215 | +#defineESIM_PORT(x) (((x) & 0xff) << 16) |
| 216 | +#defineESIM_HUB(x) (((x) & 0x7f) << 24) |
| 217 | + |
| 218 | +#defineESITF_STATUS_ACTIVE (1UL<<31) |
| 219 | +#defineESITF_STATUS_ERR (1UL<<30) |
| 220 | +#defineESITF_STATUS_BABBLE (1UL<<29) |
| 221 | +#defineESITF_STATUS_XACTERR (1UL<<28) |
| 222 | +#defineESITF_STATUS_MISSEDUF (1UL<<27) |
| 223 | +#defineESITF_LENGTH_MASK 0x03ff |
| 224 | +#defineESITF_LENGTH_SHIFT 16 |
| 225 | +#defineESITM_BP0_OFFSET_MASK 0x00000fff |
| 226 | + |
191 | 227 | /* TD control and status word defines */ |
192 | 228 |
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193 | 229 | #defineETSB_PING 0/* PING state instead of OUT */ |
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