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libraries/Arduino_H7_Video: Fix the DSI PLL configuration.#879
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With the current configuration (NDIV=125, PLLIDF=3, PLLODF=1) the DSIPLL outputs an out of spec 83MHz clock. This fix sets the output clockto the max supported clock of 62.5MHz, according to the datasheet.Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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facchinm commentedMay 13, 2024
Well spotted! This has been wrong for quite a while, since the first alpha batch of Gigas with 12MHz quartz 🤦♂️ Merging! |
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With the current configuration (NDIV=125, PLLIDF=3, PLLODF=1) the DSI PLL outputs an out of spec 83MHz clock. This fix sets the output clock to the max supported clock of 62.5MHz, according to the datasheet.
Fixes#743
Current settings:
