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Commit5638b9d

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RFC#60: add arst member to the peripheral signature.
1 parent705e307 commit5638b9d

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‎text/0060-soc-uart-peripheral.md‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,8 @@ class MySoC(wiring.Component):
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uart_phy_rx= AsyncSerialRX(uart_divisor,divisor_bits=16,pins=uart_pins)
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uart_phy_tx= AsyncSerialTX(uart_divisor,divisor_bits=16,pins=uart_pins)
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52-
m.submodules.uart_phy_rx= uart_phy_rx
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m.submodules.uart_phy_tx= uart_phy_tx
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m.submodules.uart_phy_rx=ResetInserter(uart.rx.rst)(uart_phy_rx)
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m.submodules.uart_phy_tx=ResetInserter(uart.tx.rst)(uart_phy_tx)
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m.d.comb+= [
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uart_phy_rx.divisor.eq(uart.rx.divisor),
@@ -225,6 +225,7 @@ Its members are defined as follows:
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```python3
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{
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"rst": Out(1),
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"divisor": Out(unsigned(16)),
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"symbol": In(wiring.Signature({
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"payload": Out(unsigned(symbol_width)),
@@ -236,6 +237,8 @@ Its members are defined as follows:
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}
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```
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The`rst` port is driven to 1 if`Control.enable` is 0, and 0 if`Control.enable` is 1.
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###`amaranth_soc.uart.TransmitterPHYSignature`
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The`uart.TransmitterSignature` class is a`wiring.Signature` describing the interface between the UART peripheral and its transmitter PHY, with:
@@ -245,15 +248,18 @@ Its members are defined as follows:
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```python3
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{
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"rst": Out(1),
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"divisor": Out(unsigned(16)),
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"symbol": Out(wiring.Signature({
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"payload": Out(unsigned(symbol_width)),
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"valid": Out(unsigned(1)),
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"ready": In(unsigned(1)),
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"valid": Out(1),
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"ready": In(1),
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})),
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}
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```
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The`rst` port is driven to 1 if`Control.enable` is 0, and 0 if`Control.enable` is 1.
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###`amaranth_soc.uart.ReceiverPeripheral`
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The`uart.ReceiverPeripheral` class is a`wiring.Component` implementing the receiver of an UART peripheral, with:
@@ -319,7 +325,7 @@ The `uart.Peripheral` class is a `wiring.Component` implementing an UART periphe
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- Decoupling the peripheral from the PHY allows flexibility in implementations. For example, it is easy to add FIFOs between the PHYs and the peripheral.
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- A standalone`ReceiverPeripheral` or`TransmitterPeripheral` can be instantiated.
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- The choice of a 16-bit divisor with an (otherwise) unspecified encodinggivesallows implementation freedom:
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- The choice of a 16-bit divisor with an (otherwise) unspecified encoding allows implementation freedom:
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* some may not care about a clock divisor at all (e.g. a behavioral model of an UART PHY, interfacing with a pseudo-TTY).
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* some may provide their own divisor encoding scheme (e.g. a 13-bit base value with a 3-bit scale, that can cover common frequency/baudrate combinations with a[<1% error rate](https://github.com/amaranth-lang/rfcs/files/14672989/baud.py.txt) (credit:[@whitequark](https://github.com/whitequark))).
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