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Add annotations for memory maps, wishbone and CSR primitives [updated]

#104 openedJul 30, 2025 byrobtaylor

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[WIP] Add reference-level documentation

#82 openedApr 9, 2024 byjfng • Draft

Implement RFC 60: UART peripheral.

#81 openedMar 29, 2024 byjfng • Draft

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Add annotations for memory maps, wishbone and CSR primitives.

#58 openedDec 5, 2023 byjfng

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wishbone.bus.Decoder: Only assert stb when slave is selected

#31 openedAug 23, 2021 byantonblanchard

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csr/bus: Take data width into account for register writes

#30 openedMay 14, 2021 bykbeckmann

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SRAM bus

#29 openedApr 20, 2021 byFatsie

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CSR: Export Wishbone bridge from nmigen_soc.csr

#28 openedApr 20, 2021 byFatsie

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Make optional properties return None while uninitialized.

#26 openedAug 22, 2020 byjfng

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[WIP]wishbone.Connector class

#21 openedJul 1, 2020 byFatsie

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csr.periph: add Peripheral base class.

#11 openedMar 23, 2020 byjfng

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