- Notifications
You must be signed in to change notification settings - Fork3
👾 Design and implementation of a video decoder on an Altera Cyclone V FPGA board.
License
NotificationsYou must be signed in to change notification settings
aekanman/FPGA-video-decoder
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
Design and implementation of a video decoder on an Altera Cyclone V FPGA board.
- 3 Cores
- 4 Mailboxes
- 1 Read and write DMA
- 1 2D IDCT HW accelerator
- 1 Periodic timer
- Lossless decoding
- Parallelizing the cores
- HW accelerators
- System level HW/SW co-design
- FPGA resource utilization
- Memory utilization
- Inverse discrete cosine transform (IDCT)
- Scheduling and synchronization
- Cache coherency
MIT ©Atakan Efe Kanman
About
👾 Design and implementation of a video decoder on an Altera Cyclone V FPGA board.
Topics
Resources
License
Uh oh!
There was an error while loading.Please reload this page.
Stars
Watchers
Forks
Releases
No releases published
Packages0
No packages published