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regz is a Zig code generator for microcontrollers. Vendors often publish filesthat have the details of special function registers, for ARM this is called a"System View Description" (SVD), for AVR the format is called ATDF. This tooloutputs a single file for you to start interacting with the hardware:

constregs=@import("nrf52.zig").registers;pubfnmain()void {regs.P0.PIN_CNF[17].modify(.{        .DIR=1,        .INPUT=1,        .PULL=0,        .DRIVE=0,        .SENSE=0,    });regs.P0.OUT.modify(.{ .PIN17=1 });}

NOTE: just including that file is not enough to run code on a microcontroller,this is a fairly low-level tool and it is intended that the generated code beused with something likemicrozig.

One can get SVD files from your vendor, or another good place isposborne/cmsis-svd,it's a python based SVD parser and they have a large number of files available.

For ATDF you need to unzip the appropriate atpack from theregistry.

regz targets zig master.

git clone --recursive https://github.com/ZigEmbeddedGroup/regz.gitcd regzzig build

Files provided may be either SVD or ATDF.

Provide path on command line:

regz <path-to-svd> > my-chip.zig

Provide schema via stdin, must specify the schema type:

cat my-file.svd | regz --schema svd > my-chip.zig

It seems that manufacturers are using SVD to represent registers on theirRISC-V based products despite it being an ARM standard. At best regz willgenerate the register definitions without an interrupt table (for now), if yourun into problems issues will be warmly welcomed!

TI does have another type of XML-based register schema, it is alsounimplemented but planned for support.

The main idea is to target what LLVM can target, however Zig's C backend inunderway so it's likely more exotic architectures could be reached in thefuture. If you know of any others we should look into, please make an issue!

• SVD: mostly implemented and usable for mosts MCUs, but a few finishing touches in order to suss out any bugs:
  • nested clusters
  • order generated exactly as defined in schema
  • finalize derivation of different components
  • comprehensive suite of tests
  • RISC-V interrupt table generation
• ATDF: AVR's register schema format
• insert name of Texus Insturment's register schema format for MSP430