Nov 13, 2025 · Nov 13, 2025 · Nov 10, 2025 · Nov 11, 2025 · Nov 11, 2025 · Nov 14, 2025
diff --git a/lib/Dialect/AIE/Transforms/AIEConfigToNPU.cpp b/lib/Dialect/AIE/Transforms/AIEConfigToNPU.cpp

 struct AIEConfigToNPUPass : AIEConfigToNPUBase<AIEConfigToNPUPass> {
  void runOnOperation() override {
    // Stub implementation for now
    // Will be implemented in next commit
    DeviceOp device = getOperation();
    OpBuilder builder(device);

    // For prototype: simplified implementation
    // We'll generate placeholder npu.write32 operations
    // A full implementation would:
    // 1. Load RegisterDatabase
    // 2. Resolve register names to offsets
    // 3. Merge bitfields for same register
    // 4. Calculate absolute addresses

    // For now, just emit a comment that this pass ran
    // The actual implementation will be added when we integrate
    // with a real runtime sequence and AIEX dialect

    // Collect all trace.reg operations at device level
    SmallVector<TraceRegOp> regOps;
    device.walk([&](TraceRegOp regOp) {
      // Only process reg ops that are direct children of device
      // (i.e., inlined ones, not ones still in trace.config)
      if (isa<DeviceOp>(regOp->getParentOp())) {
        regOps.push_back(regOp);
      }
    });

    // For prototype: just verify we can iterate them
    // Full implementation would generate aiex.npu.write32 here
    (void)regOps;  // Suppress unused variable warning

    // Placeholder: In full implementation, this would:
    // 1. Look up register offset from database
    // 2. Encode field value
    // 3. Merge with other writes to same register
    // 4. Generate aiex.npu.write32
  }
 };
Original file line number	Diff line number	Diff line change
Expand Up		@@ -22,8 +22,40 @@ using namespace xilinx::AIE;

		struct AIEConfigToNPUPass : AIEConfigToNPUBase<AIEConfigToNPUPass> {
		void runOnOperation() override {
		// Stub implementation for now
		// Will be implemented in next commit
		DeviceOp device = getOperation();
		OpBuilder builder(device);

		// For prototype: simplified implementation
		// We'll generate placeholder npu.write32 operations
		// A full implementation would:
		// 1. Load RegisterDatabase
		// 2. Resolve register names to offsets
		// 3. Merge bitfields for same register
		// 4. Calculate absolute addresses

		// For now, just emit a comment that this pass ran
		// The actual implementation will be added when we integrate
		// with a real runtime sequence and AIEX dialect

		// Collect all trace.reg operations at device level
		SmallVector<TraceRegOp> regOps;
		device.walk([&](TraceRegOp regOp) {
		// Only process reg ops that are direct children of device
		// (i.e., inlined ones, not ones still in trace.config)
		if (isa<DeviceOp>(regOp->getParentOp())) {
		regOps.push_back(regOp);
		}
		});

		// For prototype: just verify we can iterate them
		// Full implementation would generate aiex.npu.write32 here
		(void)regOps; // Suppress unused variable warning

		// Placeholder: In full implementation, this would:
		// 1. Look up register offset from database
		// 2. Encode field value
		// 3. Merge with other writes to same register
		// 4. Generate aiex.npu.write32
		}
		};

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