Nov 13, 2025 · Nov 13, 2025 · Nov 10, 2025 · Nov 11, 2025 · Nov 11, 2025 · Nov 14, 2025
diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.h b/include/aie/Dialect/AIE/Transforms/AIEPasses.h
 createAIEGenerateColumnControlOverlayPass();
 std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEAssignTileCtrlIDsPass();
 std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIETraceToConfigPass();
 std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEInlineTraceConfigPass();
 std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEConfigToNPUPass();

 /// Generate the code for registering passes.
 #define GEN_PASS_REGISTRATION
diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td

    This pass transforms declarative trace configurations into register-level
    specifications that can be further lowered to NPU register writes.
  }];

  let constructor = "xilinx::AIE::createAIETraceToConfigPass()";
  let dependentDialects = [
    "xilinx::AIE::AIEDialect",
  ];
 }

 def AIEInlineTraceConfig : Pass<"aie-inline-trace-config", "DeviceOp"> {
  let summary = "Inline trace configuration symbols into runtime sequence";
  let description = [{
    Replaces aie.trace.start_config operations with the actual aie.trace.reg
    operations from the referenced trace configuration symbol.

    This inlining happens within the runtime sequence context.
    Note: This pass only does semantic lowering. NPU write generation
    happens in aiex-inline-trace-config (AIEX dialect).
  }];

  let constructor = "xilinx::AIE::createAIEInlineTraceConfigPass()";
  let dependentDialects = [
    "xilinx::AIE::AIEDialect",
  ];
 }

 def AIEConfigToNPU : Pass<"aie-config-to-npu", "DeviceOp"> {
  let summary = "Lower trace register ops to NPU write operations";
  let description = [{
    Converts aie.trace.reg operations to aiex.npu.write32 operations.

    This pass resolves logical register/field names to absolute addresses
    and encoded bitfield values, then generates the final NPU register writes.
  }];

  let constructor = "xilinx::AIE::createAIEConfigToNPUPass()";
  let constructor = "xilinx::AIE::createAIETraceToConfigPass()";
  let dependentDialects = [
    "xilinx::AIE::AIEDialect",
  ];
diff --git a/include/aie/Dialect/AIEX/Transforms/AIEXPasses.h b/include/aie/Dialect/AIEX/Transforms/AIEXPasses.h
 createAIETxnToControlPacketPass();
 std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
 createAIELegalizeControlPacketPass();
 std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
 createAIEXInlineTraceConfigPass();
 std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
 createAIEXConfigToNPUPass();

 /// Generate the code for registering passes.
 #define GEN_PASS_REGISTRATION
diff --git a/include/aie/Dialect/AIEX/Transforms/AIEXPasses.td b/include/aie/Dialect/AIEX/Transforms/AIEXPasses.td
    "xilinx::AIEX::AIEXDialect",
  ];
 }

 def AIEXInlineTraceConfig : Pass<"aiex-inline-trace-config", "AIE::DeviceOp"> {
  let summary = "Inline trace configuration and generate NPU writes";
  let description = [{
    Replaces aie.trace.start_config operations by:
    1. Looking up the referenced trace.config symbol
    2. Resolving register/field names using RegisterDatabase
    3. Encoding bitfield values
    4. Merging multiple field writes to same register
    5. Generating aiex.npu.write32 operations with col/row preserved

    This pass integrates RegisterDatabase and generates NPU writes directly,
    preserving col/row information from the tile operation.
  }];

  let constructor = "xilinx::AIEX::createAIEXInlineTraceConfigPass()";
  let dependentDialects = [
    "xilinx::AIE::AIEDialect",
    "xilinx::AIEX::AIEXDialect",
  ];
 }

 def AIEXConfigToNPU : Pass<"aiex-config-to-npu", "AIE::DeviceOp"> {
  let summary = "Lower trace register ops to NPU write operations (stub)";
  let description = [{
    This pass is currently a no-op stub.
    NPU write generation for trace configuration happens in AIEXInlineTraceConfig.
    Kept for future extensibility.
  }];

  let constructor = "xilinx::AIEX::createAIEXConfigToNPUPass()";
  let dependentDialects = [
    "xilinx::AIE::AIEDialect",
    "xilinx::AIEX::AIEXDialect",
  ];
 }

 #endif
diff --git a/lib/Dialect/AIE/Transforms/CMakeLists.txt b/lib/Dialect/AIE/Transforms/CMakeLists.txt
  AIELowerCascadeFlows.cpp
  AIEGenerateColumnControlOverlay.cpp
  AIETraceToConfig.cpp
  AIEInlineTraceConfig.cpp
  AIEConfigToNPU.cpp
  ADDITIONAL_HEADER_DIRS
  ${AIE_BINARY_DIR}/include

diff --git a/lib/Dialect/AIEX/Transforms/AIEConfigToNPU.cpp b/lib/Dialect/AIEX/Transforms/AIEConfigToNPU.cpp
 //===- AIEConfigToNPU.cpp ---------------------------------------*- C++ -*-===//
 //
 // This file is licensed under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 // Copyright (C) 2025, Advanced Micro Devices, Inc.
 //
 //===----------------------------------------------------------------------===//
 // Pass to lower trace.reg to aiex.npu.write32
 // NOTE: This pass is now a stub. NPU generation moved to AIEInlineTraceConfig.
 //===----------------------------------------------------------------------===//

 #include "aie/Dialect/AIE/IR/AIEDialect.h"
 #include "aie/Dialect/AIEX/Transforms/AIEXPasses.h"

 #include "mlir/Pass/Pass.h"

 using namespace mlir;
 using namespace xilinx;
 using namespace xilinx::AIEX;

 struct AIEConfigToNPUPass : AIEXConfigToNPUBase<AIEConfigToNPUPass> {
  void runOnOperation() override {
    // This pass is now a no-op.
    // NPU write generation happens in AIEInlineTraceConfig (Pass 2).
    // Keeping this pass for future extensibility.
    return;
  }
 };

 std::unique_ptr<OperationPass<AIE::DeviceOp>>
 xilinx::AIEX::createAIEXConfigToNPUPass() {
  return std::make_unique<AIEConfigToNPUPass>();
 }
diff --git a/lib/Dialect/AIEX/Transforms/AIEInlineTraceConfig.cpp b/lib/Dialect/AIEX/Transforms/AIEInlineTraceConfig.cpp
 //===- AIEInlineTraceConfig.cpp ---------------------------------*- C++ -*-===//
 //
 // This file is licensed under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 // Copyright (C) 2025, Advanced Micro Devices, Inc.
 //
 //===----------------------------------------------------------------------===//
 // Pass to inline trace.start_config and generate npu.write32
 //===----------------------------------------------------------------------===//

 #include "aie/Dialect/AIE/IR/AIEDialect.h"
 #include "aie/Dialect/AIE/IR/AIERegisterDatabase.h"
 #include "aie/Dialect/AIEX/IR/AIEXDialect.h"
 #include "aie/Dialect/AIEX/Transforms/AIEXPasses.h"

 #include "mlir/IR/Attributes.h"
 #include "mlir/Pass/Pass.h"

 using namespace mlir;
 using namespace xilinx;
 using namespace xilinx::AIE;
 using namespace xilinx::AIEX;

 struct AIEInlineTraceConfigPass : AIEXInlineTraceConfigBase<AIEInlineTraceConfigPass> {
  void runOnOperation() override {
    AIE::DeviceOp device = getOperation();

    // Load RegisterDatabase for AIE2
    auto regDb = RegisterDatabase::loadAIE2();
    if (!regDb) {
      device.emitError("Failed to load register database");
      return signalPassFailure();
    }

    // // Load AIEX dialect (it's registered in aie-opt)
    // device->getContext()->getOrLoadDialect<AIEX::AIEXDialect>();

    // Collect all trace.start_config operations
    SmallVector<TraceStartConfigOp> startConfigs;
    device.walk([&](TraceStartConfigOp startConfig) {
      startConfigs.push_back(startConfig);
    });

    for (auto startConfig : startConfigs) {
      OpBuilder builder(startConfig);

      // Lookup the trace config symbol
      auto configSymbolName = startConfig.getTraceConfig();
      auto configOp = dyn_cast_or_null<TraceConfigOp>(
        SymbolTable::lookupNearestSymbolFrom(device,
          builder.getStringAttr(configSymbolName))
      );

      if (!configOp) {
        startConfig.emitError("trace config symbol '")
          << configSymbolName << "' not found";
        return signalPassFailure();
      }

      // Get tile and extract col/row
      auto tile = configOp.getTile();
      auto tileOp = dyn_cast<TileOp>(tile.getDefiningOp());
      if (!tileOp) {
        startConfig.emitError("tile operand must be a TileOp");
        return signalPassFailure();
      }

      int col = tileOp.getCol();
      int row = tileOp.getRow();

      // Determine module based on tile row
      std::string module = "CORE_MODULE";
      if (row == 0) module = "PL_MODULE";
      else if (row == 1) module = "MEM_TILE_MODULE";

      // Group register writes by offset for merging
      std::map<uint32_t, uint32_t> mergedValues;
      std::map<uint32_t, TraceRegOp> firstRegOp;

      // Process all trace.reg operations in the config
      for (auto &op : configOp.getBody().getOps()) {
        auto regOp = dyn_cast<TraceRegOp>(op);
        if (!regOp) continue;

        // Look up register
        auto regName = regOp.getRegName().str();
        auto* regInfo = regDb->lookupRegister(regName, module);
        if (!regInfo) {
          regOp.emitWarning("Register '") << regName << "' not found in module " << module;
          continue;
        }

        // Look up field
        auto fieldName = regOp.getField().str();
        auto* fieldInfo = regInfo->getField(fieldName);
        if (!fieldInfo) {
          regOp.emitWarning("Field '") << fieldName << "' not found in register " << regName;
          continue;
        }

        // Encode value
        uint32_t encodedValue = 0;
        auto value = regOp.getValue();

        if (auto intAttr = llvm::dyn_cast<IntegerAttr>(value)) {
          // Integer value
          encodedValue = regDb->encodeFieldValue(*fieldInfo, intAttr.getInt());
        } else if (auto strAttr = llvm::dyn_cast<StringAttr>(value)) {
          // String value - resolve as event
          std::string strVal = strAttr.getValue().str();
          auto eventCode = regDb->lookupEvent(strVal, "core");
          if (eventCode) {
            encodedValue = regDb->encodeFieldValue(*fieldInfo, *eventCode);
          }
        }

        // Merge into accumulated value
        mergedValues[regInfo->offset] |= encodedValue;
        if (firstRegOp.find(regInfo->offset) == firstRegOp.end()) {
          firstRegOp[regInfo->offset] = regOp;
        }
      }

      // Generate aiex.npu.write32 operations with col/row
      for (auto& [offset, value] : mergedValues) {
        builder.create<AIEX::NpuWrite32Op>(
          firstRegOp[offset].getLoc(),
          builder.getUI32IntegerAttr(offset),
          builder.getUI32IntegerAttr(value),
          nullptr,  // buffer
          builder.getI32IntegerAttr(col),  // column
          builder.getI32IntegerAttr(row)   // row
        );
      }

      // Remove the start_config invocation
      startConfig.erase();
    }
  }
 };

 std::unique_ptr<OperationPass<AIE::DeviceOp>>
 xilinx::AIEX::createAIEXInlineTraceConfigPass() {
  return std::make_unique<AIEInlineTraceConfigPass>();
 }
diff --git a/lib/Dialect/AIEX/Transforms/CMakeLists.txt b/lib/Dialect/AIEX/Transforms/CMakeLists.txt
  AIELowerSetLock.cpp
  AIETransformBfpTypes.cpp
  AIETxnToControlPacket.cpp
  AIEInlineTraceConfig.cpp
  AIEConfigToNPU.cpp
  ADDITIONAL_HEADER_DIRS
  ${AIE_BINARY_DIR}/include
Original file line number	Diff line number	Diff line change
Expand Up		@@ -57,8 +57,6 @@ std::unique_ptr<mlir::OperationPass<DeviceOp>>
		createAIEGenerateColumnControlOverlayPass();
		std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEAssignTileCtrlIDsPass();
		std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIETraceToConfigPass();
		std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEInlineTraceConfigPass();
		std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEConfigToNPUPass();

		/// Generate the code for registering passes.
		#define GEN_PASS_REGISTRATION
Expand Down
Original file line number	Diff line number	Diff line change
Expand Up		@@ -382,39 +382,12 @@ def AIETraceToConfig : Pass<"aie-trace-to-config", "DeviceOp"> {

		This pass transforms declarative trace configurations into register-level
		specifications that can be further lowered to NPU register writes.
		}];

		let constructor = "xilinx::AIE::createAIETraceToConfigPass()";
		let dependentDialects = [
		"xilinx::AIE::AIEDialect",
		];
		}

		def AIEInlineTraceConfig : Pass<"aie-inline-trace-config", "DeviceOp"> {
		let summary = "Inline trace configuration symbols into runtime sequence";
		let description = [{
		Replaces aie.trace.start_config operations with the actual aie.trace.reg
		operations from the referenced trace configuration symbol.

		This inlining happens within the runtime sequence context.
		Note: This pass only does semantic lowering. NPU write generation
		happens in aiex-inline-trace-config (AIEX dialect).
		}];

		let constructor = "xilinx::AIE::createAIEInlineTraceConfigPass()";
		let dependentDialects = [
		"xilinx::AIE::AIEDialect",
		];
		}

		def AIEConfigToNPU : Pass<"aie-config-to-npu", "DeviceOp"> {
		let summary = "Lower trace register ops to NPU write operations";
		let description = [{
		Converts aie.trace.reg operations to aiex.npu.write32 operations.

		This pass resolves logical register/field names to absolute addresses
		and encoded bitfield values, then generates the final NPU register writes.
		}];

		let constructor = "xilinx::AIE::createAIEConfigToNPUPass()";
		let constructor = "xilinx::AIE::createAIETraceToConfigPass()";
		let dependentDialects = [
		"xilinx::AIE::AIEDialect",
		];
Expand Down
Original file line number	Diff line number	Diff line change
Expand Up		@@ -50,6 +50,10 @@ std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
		createAIETxnToControlPacketPass();
		std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
		createAIELegalizeControlPacketPass();
		std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
		createAIEXInlineTraceConfigPass();
		std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
		createAIEXConfigToNPUPass();

		/// Generate the code for registering passes.
		#define GEN_PASS_REGISTRATION
Expand Down
Original file line number	Diff line number	Diff line change
Expand Up		@@ -254,4 +254,41 @@ def AIELegalizeControlPacket : Pass<"aie-legalize-ctrl-packet", "AIE::DeviceOp">
		"xilinx::AIEX::AIEXDialect",
		];
		}

		def AIEXInlineTraceConfig : Pass<"aiex-inline-trace-config", "AIE::DeviceOp"> {
		let summary = "Inline trace configuration and generate NPU writes";
		let description = [{
		Replaces aie.trace.start_config operations by:
		1. Looking up the referenced trace.config symbol
		2. Resolving register/field names using RegisterDatabase
		3. Encoding bitfield values
		4. Merging multiple field writes to same register
		5. Generating aiex.npu.write32 operations with col/row preserved

		This pass integrates RegisterDatabase and generates NPU writes directly,
		preserving col/row information from the tile operation.
		}];

		let constructor = "xilinx::AIEX::createAIEXInlineTraceConfigPass()";
		let dependentDialects = [
		"xilinx::AIE::AIEDialect",
		"xilinx::AIEX::AIEXDialect",
		];
		}

		def AIEXConfigToNPU : Pass<"aiex-config-to-npu", "AIE::DeviceOp"> {
		let summary = "Lower trace register ops to NPU write operations (stub)";
		let description = [{
		This pass is currently a no-op stub.
		NPU write generation for trace configuration happens in AIEXInlineTraceConfig.
		Kept for future extensibility.
		}];

		let constructor = "xilinx::AIEX::createAIEXConfigToNPUPass()";
		let dependentDialects = [
		"xilinx::AIE::AIEDialect",
		"xilinx::AIEX::AIEXDialect",
		];
		}

		#endif
Original file line number	Diff line number	Diff line change
Expand Up		@@ -27,8 +27,6 @@ add_mlir_dialect_library(
		AIELowerCascadeFlows.cpp
		AIEGenerateColumnControlOverlay.cpp
		AIETraceToConfig.cpp
		AIEInlineTraceConfig.cpp
		AIEConfigToNPU.cpp
		ADDITIONAL_HEADER_DIRS
		${AIE_BINARY_DIR}/include

Expand Down
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,35 @@
		//===- AIEConfigToNPU.cpp ---------------------------------------- C++ --===//
		//
		// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
		// See https://llvm.org/LICENSE.txt for license information.
		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		//
		// Copyright (C) 2025, Advanced Micro Devices, Inc.
		//
		//===----------------------------------------------------------------------===//
		// Pass to lower trace.reg to aiex.npu.write32
		// NOTE: This pass is now a stub. NPU generation moved to AIEInlineTraceConfig.
		//===----------------------------------------------------------------------===//

		#include "aie/Dialect/AIE/IR/AIEDialect.h"
		#include "aie/Dialect/AIEX/Transforms/AIEXPasses.h"

		#include "mlir/Pass/Pass.h"

		using namespace mlir;
		using namespace xilinx;
		using namespace xilinx::AIEX;

		struct AIEConfigToNPUPass : AIEXConfigToNPUBase<AIEConfigToNPUPass> {
		void runOnOperation() override {
		// This pass is now a no-op.
		// NPU write generation happens in AIEInlineTraceConfig (Pass 2).
		// Keeping this pass for future extensibility.
		return;
		}
		};

		std::unique_ptr<OperationPass<AIE::DeviceOp>>
		xilinx::AIEX::createAIEXConfigToNPUPass() {
		return std::make_unique<AIEConfigToNPUPass>();
		}
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,147 @@
		//===- AIEInlineTraceConfig.cpp ---------------------------------- C++ --===//
		//
		// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
		// See https://llvm.org/LICENSE.txt for license information.
		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
		//
		// Copyright (C) 2025, Advanced Micro Devices, Inc.
		//
		//===----------------------------------------------------------------------===//
		// Pass to inline trace.start_config and generate npu.write32
		//===----------------------------------------------------------------------===//

		#include "aie/Dialect/AIE/IR/AIEDialect.h"
		#include "aie/Dialect/AIE/IR/AIERegisterDatabase.h"
		#include "aie/Dialect/AIEX/IR/AIEXDialect.h"
		#include "aie/Dialect/AIEX/Transforms/AIEXPasses.h"

		#include "mlir/IR/Attributes.h"
		#include "mlir/Pass/Pass.h"

		using namespace mlir;
		using namespace xilinx;
		using namespace xilinx::AIE;
		using namespace xilinx::AIEX;

		struct AIEInlineTraceConfigPass : AIEXInlineTraceConfigBase<AIEInlineTraceConfigPass> {
		void runOnOperation() override {
		AIE::DeviceOp device = getOperation();

		// Load RegisterDatabase for AIE2
		auto regDb = RegisterDatabase::loadAIE2();
		if (!regDb) {
		device.emitError("Failed to load register database");
		return signalPassFailure();
		}

		// // Load AIEX dialect (it's registered in aie-opt)
		// device->getContext()->getOrLoadDialect<AIEX::AIEXDialect>();

		// Collect all trace.start_config operations
		SmallVector<TraceStartConfigOp> startConfigs;
		device.walk([&](TraceStartConfigOp startConfig) {
		startConfigs.push_back(startConfig);
		});

		for (auto startConfig : startConfigs) {
		OpBuilder builder(startConfig);

		// Lookup the trace config symbol
		auto configSymbolName = startConfig.getTraceConfig();
		auto configOp = dyn_cast_or_null<TraceConfigOp>(
		SymbolTable::lookupNearestSymbolFrom(device,
		builder.getStringAttr(configSymbolName))
		);

		if (!configOp) {
		startConfig.emitError("trace config symbol '")
		<< configSymbolName << "' not found";
		return signalPassFailure();
		}

		// Get tile and extract col/row
		auto tile = configOp.getTile();
		auto tileOp = dyn_cast<TileOp>(tile.getDefiningOp());
		if (!tileOp) {
		startConfig.emitError("tile operand must be a TileOp");
		return signalPassFailure();
		}

		int col = tileOp.getCol();
		int row = tileOp.getRow();

		// Determine module based on tile row
		std::string module = "CORE_MODULE";
		if (row == 0) module = "PL_MODULE";
		else if (row == 1) module = "MEM_TILE_MODULE";

		// Group register writes by offset for merging
		std::map<uint32_t, uint32_t> mergedValues;
		std::map<uint32_t, TraceRegOp> firstRegOp;

		// Process all trace.reg operations in the config
		for (auto &op : configOp.getBody().getOps()) {
		auto regOp = dyn_cast<TraceRegOp>(op);
		if (!regOp) continue;

		// Look up register
		auto regName = regOp.getRegName().str();
		auto* regInfo = regDb->lookupRegister(regName, module);
		if (!regInfo) {
		regOp.emitWarning("Register '") << regName << "' not found in module " << module;
		continue;
		}

		// Look up field
		auto fieldName = regOp.getField().str();
		auto* fieldInfo = regInfo->getField(fieldName);
		if (!fieldInfo) {
		regOp.emitWarning("Field '") << fieldName << "' not found in register " << regName;
		continue;
		}

		// Encode value
		uint32_t encodedValue = 0;
		auto value = regOp.getValue();

		if (auto intAttr = llvm::dyn_cast<IntegerAttr>(value)) {
		// Integer value
		encodedValue = regDb->encodeFieldValue(*fieldInfo, intAttr.getInt());
		} else if (auto strAttr = llvm::dyn_cast<StringAttr>(value)) {
		// String value - resolve as event
		std::string strVal = strAttr.getValue().str();
		auto eventCode = regDb->lookupEvent(strVal, "core");
		if (eventCode) {
		encodedValue = regDb->encodeFieldValue(fieldInfo, eventCode);
		}
		}

		// Merge into accumulated value
		mergedValues[regInfo->offset] \|= encodedValue;
		if (firstRegOp.find(regInfo->offset) == firstRegOp.end()) {
		firstRegOp[regInfo->offset] = regOp;
		}
		}

		// Generate aiex.npu.write32 operations with col/row
		for (auto& [offset, value] : mergedValues) {
		builder.create<AIEX::NpuWrite32Op>(
		firstRegOp[offset].getLoc(),
		builder.getUI32IntegerAttr(offset),
		builder.getUI32IntegerAttr(value),
		nullptr, // buffer
		builder.getI32IntegerAttr(col), // column
		builder.getI32IntegerAttr(row) // row
		);
		}

		// Remove the start_config invocation
		startConfig.erase();
		}
		}
		};

		std::unique_ptr<OperationPass<AIE::DeviceOp>>
		xilinx::AIEX::createAIEXInlineTraceConfigPass() {
		return std::make_unique<AIEInlineTraceConfigPass>();
		}
Original file line number	Diff line number	Diff line change
Expand Up		@@ -22,6 +22,8 @@ add_mlir_dialect_library(AIEXTransforms
		AIELowerSetLock.cpp
		AIETransformBfpTypes.cpp
		AIETxnToControlPacket.cpp
		AIEInlineTraceConfig.cpp
		AIEConfigToNPU.cpp
		ADDITIONAL_HEADER_DIRS
		${AIE_BINARY_DIR}/include

Expand Down