Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

- Renamed trace_events_enum.py to trace_events package with per-architecture modules- Changed from single file to package: aie.utils.trace_events.{aie,aie2,aie2p}- Renamed PLEvent to ShimTileEvent to match expected usage- Generate files during build into build/regdb/ directory instead of manually generating- Copy generated files to Python package directory during build- Install generated files along with checked-in __init__.py- Update all imports to use new package structure- Conditionally emit UCEvent enum only when events are defined (e.g. aie2ps in future)- Emit unified events.json into build/regdb for compiler ingest (for future work)- Map aieml architecture to aie2 for Python module namingFill enum value gaps with reserved placeholdersThe generator now fills gaps in enum values with rsvd_XX placeholdersto ensure continuous numbering from min to max value. This matches thebehavior of the original manually-generated file and ensures that allhardware event codes are represented in the enum, even if they arereserved or undefined.Example: If events 0-53 and 55-127 are defined, value 54 getsplaceholder rsvd_54 to maintain continuity.Fixes comparison with original trace_events_enum.py file.

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>Co-authored-by: fifield <800843+fifield@users.noreply.github.com>Co-authored-by: Jeff Fifield <jeff.fifield@amd.com>Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>

- Add generate_events_tablegen.py to create TableGen enum definitions  from aie-rt event headers- Update AIE dialect CMakeLists to generate AIEEvents*.td.inc files  during build process- Include generated event enums in AIEAttrs.td- Add proper CMake dependencies to ensure enums are generated before  they are needed by tablegenThis allows the AIE dialect to emit C++ enum classes for all eventtypes (CoreEvent, MemEvent, ShimTileEvent, MemTileEvent) across allAIE architectures (AIE, AIE2, AIE2P).

- Created AIETraceAttrs.td with TraceModeAttr, TracePacketTypeAttr, TraceEventAttr- Created AIETraceOps.td with trace operations:  - aie.trace (symbol operation)  - aie.trace.mode, aie.trace.event, aie.trace.packet  - aie.trace.start, aie.trace.stop  - aie.trace.config, aie.trace.reg (intermediate ops)  - aie.trace.start_config (runtime invocation)- Implemented basic C++ verifiers in AIETraceOps.cpp- Updated AIEAttrs.td and AIEOps.td to include trace definitions- Updated lib/Dialect/AIE/IR/CMakeLists.txt to build AIETraceOps.cpp- Added parsing test that validates operations parse correctly- Test passes: operations parse and print correctly

- Created test_trace_verify.mlir with negative tests:  - Too many events (>8)  - Packet ID out of range (0 and 32)  - Start/stop events missing parameters  - Start/stop events with conflicting parameters- All verifiers working correctly- Tests pass successfully

- Created AIERegisterDatabase.h with BitFieldInfo, RegisterInfo, EventInfo structs- Implemented AIERegisterDatabase.cpp with JSON parsing for:  - Register database (utils/aie_registers_aie2.json)  - Event database (utils/events_database.json)- Key features:  - lookupRegister(name, module) - finds register by name and module  - lookupEvent(name, module) - finds event code by name and module  - encodeFieldValue(field, value) - encodes value into bitfield- Uses module::name keys to handle duplicate register names across modules- Compiles successfully and links with AIE dialect

- Added pass definitions to AIEPasses.td for all three trace passes- Updated AIEPasses.h with pass creation function declarations- Implemented AIETraceToConfig.cpp:  - Converts aie.trace → aie.trace.config  - Emits aie.trace.reg operations for each register field  - Handles Trace_Control0 (mode, start/stop events)  - Handles Trace_Control1 (packet ID, packet type)  - Handles Trace_Event0/1 (event slots 0-7)  - Updates trace.start_config symbol references- Created stub implementations for AIEInlineTraceConfig and AIEConfigToNPU- Added test_trace_to_config.mlir that validates transformation- Test passes: trace ops correctly lowered to config ops

- Implemented AIEInlineTraceConfig.cpp:  - Finds all aie.trace.start_config operations  - Looks up referenced trace.config symbol  - Clones all aie.trace.reg operations to call site  - Removes trace.start_config invocation- Relaxed parent constraint on aie.trace.reg to allow DeviceOp parent  (needed for inlined reg ops)- Added test_inline_trace_config.mlir- Test passes: trace.reg ops successfully inlined

- Implemented AIEConfigToNPU.cpp with prototype stub- Pass collects inlined trace.reg operations- Placeholder for full implementation that would:  - Load RegisterDatabase  - Resolve register names to offsets  - Encode bitfield values  - Merge writes to same register  - Generate aiex.npu.write32 operations- Compiles successfully

- Created test_trace_end_to_end.mlir demonstrating complete pipeline- Tests full transformation: aie.trace → aie.trace.config → inlined aie.trace.reg- Validates:  - High-level trace configuration with 4 events  - Mode, packet routing, start/stop events  - Correct lowering through both passes  - Symbol references updated correctly  - Register specifications generated for all fields- Test passes: complete pipeline working end-to-end

- Enhanced aie.trace.reg to include optional tile operand- Updated AIETraceToConfig to pass nullptr for tile (parent has it)- Updated AIEInlineTraceConfig to pass tile reference when cloning- Implemented full AIEConfigToNPU with:  - RegisterDatabase loading and integration  - Register name → offset resolution  - Event name → event code resolution  - Bitfield value encoding  - Register write merging (multiple fields → single register)  - Absolute address calculation  - aiex.npu.write32 generation (when AIEX dialect available)- Pass validates register/field lookups work correctly- Demonstrates complete lowering pipeline infrastructureNote: NPU write generation requires AIEX dialect to be pre-loaded.This will be addressed in production integration.

PROBLEM FIXED:- trace.reg with 'for %tile' lost col/row information- Inlined trace.reg at device level was fragileSOLUTION:- Removed tile operand from trace.reg (now only in trace.config)- Simplified parent constraint: trace.reg only in TraceConfigOp- Moved RegisterDatabase integration from Pass 3 to Pass 2- Pass 2 now generates npu.write32 directly with col/row from tile- Pass 3 is now a no-op (kept for extensibility)BENEFITS:- Col/row extracted immediately during inlining (not lost)- Cleaner IR (no intermediate trace.reg at device level)- Two-pass pipeline instead of three- npu.write32 has explicit column/row attributesThis fixes the architectural issue identified in code review.

PROBLEM: AIEX dialect couldn't be loaded during AIE pass executionSOLUTION: Move NPU-generating passes to AIEX dialect where they belong- Moved AIEInlineTraceConfig.cpp to lib/Dialect/AIEX/Transforms/- Moved AIEConfigToNPU.cpp to lib/Dialect/AIEX/Transforms/- Updated pass definitions in AIEXPasses.td- Removed from AIEPasses.td- Updated CMakeLists for both dialects- Updated pass registration headers- Fixed namespaces (AIEX, not AIE)RESULT: npu.write32 generation now works!- Pass renamed: aie-inline-trace-config → aiex-inline-trace-config- Pass renamed: aie-config-to-npu → aiex-config-to-npu- Col/row preserved in npu.write32 operations- RegisterDatabase integration functional- Bitfield merging workingExample output:aiex.npu.write32 {address=0xB40D0, column=0, row=2, value=0x1E2E0001}This is the correct architectural placement: AIEX depends on AIE.

- Moved test_inline_trace_config.mlir to test/Dialect/AIEX/trace/- Moved test_trace_end_to_end.mlir to test/Dialect/AIEX/trace/- Updated pass name: aie-inline-trace-config → aiex-inline-trace-config- Added CHECK for aiex.npu.write32 operations- Verified col/row attributes are preserved- Both tests pass successfullyTest organization:- AIE tests: parse, verify, trace-to-config (AIE dialect operations)- AIEX tests: inline-trace-config, end-to-end (NPU generation)This reflects the correct architectural separation.

- Added aiex.runtime_sequence wrapper to both tests- Shows proper usage: trace.start_config inside runtime_sequence- Tests validate npu.write32 generation within runtime context- All tests passing with correct architectural patternThis demonstrates the intended usage pattern where trace configurationis invoked from within a runtime sequence.

Implement aie.trace.port operation for hardware stream switch port monitoring:- Extend AIETargetModel with port mapping API (getStreamSwitchPortIndex, isValidStreamSwitchPort)- Add AIE_TracePortOp to AIETraceOps.td with slot (0-7), port, channel, master attributes- Implement TracePortOp::verify() with duplicate slot detection and port validation- Extend RegisterDatabase with resolvePortValue() for PORT:CHANNEL string parsing- Update AIETraceToConfig to process TracePortOp and generate register writes- Update AIETracePackRegWrites to resolve PORT:CHANNEL to hardware indices- Add comprehensive test suite: parse, verify, lowering, end-to-end testsTarget registers: Stream_Switch_Event_Port_Selection_0/1Enables monitoring of up to 8 stream switch ports with PORT_RUNNING, PORT_IDLE, PORT_STALLED, PORT_TLAST events.Note: Current implementation uses stub port mappings - actual hardware tables needed.

Use DMAChannelDir enum instead of boolean for stream switch port direction:- S2MM (Stream-to-Memory-Mapped) = master port (value 1)- MM2S (Memory-Mapped-to-Stream) = slave port (value 0)This provides clearer semantics matching the hardware's DMA channel directionnaming convention and makes the port direction more explicit in the IR.Updated:- AIE_TracePortOp: Changed 'master' attribute from BoolAttr to DMAChannelDir 'direction'- TracePortOp::verify(): Convert DMAChannelDir to bool for TargetModel API- AIETraceToConfig Pass 1: Convert direction enum to master/slave value- All test files: Updated syntax from 'master=true/false' to 'direction=S2MM/MM2S'