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Commit922ebdb

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[AIEX] Factor out common register logic into AIEBaseRegisterInfo.td
1 parentac6dbe7 commit922ebdb

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7 files changed

+158
-132
lines changed

7 files changed

+158
-132
lines changed

‎llvm/lib/Target/AIE/AIE2GenRegisterInfo.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
//===----------------------------------------------------------------------===//
1616
//* Automatically generated file, do not edit! *
1717

18+
include "AIEBaseRegisterInfo.td"
19+
1820
let Namespace = "AIE2" in {
1921

2022
class AIE2Reg<string n> : Register<n> {
@@ -27,13 +29,11 @@ let Namespace = "AIE2" in {
2729
}
2830

2931
class AIE2RegisterClass <int size, int align, list<ValueType> regTypes, dag reglist, RegAltNameIndex idx = NoRegAltName> :
30-
RegisterClass<"AIE2", regTypes, /*alignment*/size, reglist, idx> {
32+
AIEBaseRegisterClass<"AIE2", regTypes, /*alignment*/size, reglist, idx> {
3133
dag Regs = reglist;
3234
let RegInfos = RegInfoByHwMode<
3335
[DefaultMode],
3436
[RegInfo</*size*/size, /*spill size*/size, /*spill alignment*/align>]>;
35-
let DecodeZeroBitOperand = true;
36-
let hasCompleteDecoder = false;
3737
}
3838

3939
class AIE2ScalarRegisterClass<dag reglist, RegAltNameIndex idx = NoRegAltName>
@@ -68,23 +68,23 @@ class AIE2RegisterClass <int size, int align, list<ValueType> regTypes, dag regl
6868
AIE2RegisterClass<1024, 256, [v16i64], reglist>;
6969

7070
class AIE220BitRegisterClass <dag reglist, RegAltNameIndex idx = NoRegAltName> :
71-
RegisterClass<"AIE2", [i20], /*alignment*/ 32, reglist, idx> {
71+
AIEBaseRegisterClass<"AIE2", [i20], /*alignment*/ 32, reglist, idx> {
7272
dag Regs = reglist;
7373
let RegInfos = RegInfoByHwMode<
7474
[DefaultMode],
7575
[RegInfo</*size*/20, /*spill size*/32, /*spill alignment*/32>]>;
7676
}
7777

7878
class AIE2Dim2DRegisterClass <dag reglist, RegAltNameIndex idx = NoRegAltName> :
79-
RegisterClass<"AIE2", [i20], /*alignment*/ 32, reglist, idx> {
79+
AIEBaseRegisterClass<"AIE2", [i20], /*alignment*/ 32, reglist, idx> {
8080
dag Regs = reglist;
8181
let RegInfos = RegInfoByHwMode<
8282
[DefaultMode],
8383
[RegInfo</*size*/80, /*spill size*/128, /*spill alignment*/32>]>;
8484
}
8585

8686
class AIE2Dim3DRegisterClass <dag reglist, RegAltNameIndex idx = NoRegAltName> :
87-
RegisterClass<"AIE2", [i20], /*alignment*/ 32, reglist, idx> {
87+
AIEBaseRegisterClass<"AIE2", [i20], /*alignment*/ 32, reglist, idx> {
8888
dag Regs = reglist;
8989
let RegInfos = RegInfoByHwMode<
9090
[DefaultMode],

‎llvm/lib/Target/AIE/AIE2PRegOperandDef.td‎

Lines changed: 59 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -4,71 +4,66 @@
44
// See https://llvm.org/LICENSE.txt for license information.
55
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
66
//
7-
// (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
7+
// (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
88
//
99
//===----------------------------------------------------------------------===//
1010
//* Automatically generated file, do not edit! *
1111

12-
class AIE2PRegisterOperand<RegisterClass c> : RegisterOperand<c> {
13-
let EncoderMethod = "get" # c # OpValue;
14-
let hasCompleteDecoder = false;
15-
}
16-
17-
def OP_mWa : AIE2PRegisterOperand<mWa>;
18-
def OP_mXm : AIE2PRegisterOperand<mXm>;
19-
def OP_mCMm : AIE2PRegisterOperand<mCMm>;
20-
def OP_mQEXsm : AIE2PRegisterOperand<mQEXsm>;
21-
def OP_mEs : AIE2PRegisterOperand<mEs>;
22-
def OP_mAguSrc : AIE2PRegisterOperand<mAguSrc>;
23-
def OP_mQXsb : AIE2PRegisterOperand<mQXsb>;
24-
def OP_mEhm : AIE2PRegisterOperand<mEhm>;
25-
def OP_mLdaScl : AIE2PRegisterOperand<mLdaScl>;
26-
def OP_mQQsm : AIE2PRegisterOperand<mQQsm>;
27-
def OP_mWs : AIE2PRegisterOperand<mWs>;
28-
def OP_mXw : AIE2PRegisterOperand<mXw>;
29-
def OP_mAguDst : AIE2PRegisterOperand<mAguDst>;
30-
def OP_mEXm : AIE2PRegisterOperand<mEXm>;
31-
def OP_mQXsa : AIE2PRegisterOperand<mQXsa>;
32-
def OP_mDm : AIE2PRegisterOperand<mDm>;
33-
def OP_mQQss : AIE2PRegisterOperand<mQQss>;
34-
def OP_mQXsm : AIE2PRegisterOperand<mQXsm>;
35-
def OP_mShflBMDst : AIE2PRegisterOperand<mShflBMDst>;
36-
def OP_mBMm : AIE2PRegisterOperand<mBMm>;
37-
def OP_mMvBMXDst : AIE2PRegisterOperand<mMvBMXDst>;
38-
def OP_mShflXDst : AIE2PRegisterOperand<mShflXDst>;
39-
def OP_mMvSclDst : AIE2PRegisterOperand<mMvSclDst>;
40-
def OP_mMcdXSrc : AIE2PRegisterOperand<mMcdXSrc>;
41-
def OP_mEXn : AIE2PRegisterOperand<mEXn>;
42-
def OP_mMvSclDstCg : AIE2PRegisterOperand<mMvSclDstCg>;
43-
def OP_mSclMS : AIE2PRegisterOperand<mSclMS>;
44-
def OP_mXn : AIE2PRegisterOperand<mXn>;
45-
def OP_mBMSm : AIE2PRegisterOperand<mBMSm>;
46-
def OP_mXv : AIE2PRegisterOperand<mXv>;
47-
def OP_mWb : AIE2PRegisterOperand<mWb>;
48-
def OP_mMvBMXSrc : AIE2PRegisterOperand<mMvBMXSrc>;
49-
def OP_mAluCg : AIE2PRegisterOperand<mAluCg>;
50-
def OP_mEXw : AIE2PRegisterOperand<mEXw>;
51-
def OP_mXs : AIE2PRegisterOperand<mXs>;
52-
def OP_mEXs : AIE2PRegisterOperand<mEXs>;
53-
def OP_mCMs : AIE2PRegisterOperand<mCMs>;
54-
def OP_mFifoHLReg : AIE2PRegisterOperand<mFifoHLReg>;
55-
def OP_mSRm : AIE2PRegisterOperand<mSRm>;
56-
def OP_mElm : AIE2PRegisterOperand<mElm>;
57-
def OP_mQEXsw : AIE2PRegisterOperand<mQEXsw>;
58-
def OP_mQQsa : AIE2PRegisterOperand<mQQsa>;
59-
def OP_mEXv : AIE2PRegisterOperand<mEXv>;
60-
def OP_mXa : AIE2PRegisterOperand<mXa>;
61-
def OP_mWm : AIE2PRegisterOperand<mWm>;
62-
def OP_mMvSclSrc : AIE2PRegisterOperand<mMvSclSrc>;
63-
def OP_mQEXsa : AIE2PRegisterOperand<mQEXsa>;
64-
def OP_mCRm : AIE2PRegisterOperand<mCRm>;
65-
def OP_mSclSt : AIE2PRegisterOperand<mSclSt>;
66-
def OP_mMcdBMSrc : AIE2PRegisterOperand<mMcdBMSrc>;
67-
def OP_mQXsw : AIE2PRegisterOperand<mQXsw>;
68-
def OP_mEXa : AIE2PRegisterOperand<mEXa>;
69-
def OP_mQEXsb : AIE2PRegisterOperand<mQEXsb>;
70-
def OP_mLdaCg : AIE2PRegisterOperand<mLdaCg>;
71-
def OP_mFl2FxSrc_W : AIE2PRegisterOperand<mFl2FxSrc_W>;
72-
def OP_mXb : AIE2PRegisterOperand<mXb>;
73-
def OP_mBMs : AIE2PRegisterOperand<mBMs>;
74-
def OP_mEXb : AIE2PRegisterOperand<mEXb>;
12+
def OP_mWa : AIEBaseRegisterOperand<mWa>;
13+
def OP_mXm : AIEBaseRegisterOperand<mXm>;
14+
def OP_mCMm : AIEBaseRegisterOperand<mCMm>;
15+
def OP_mQEXsm : AIEBaseRegisterOperand<mQEXsm>;
16+
def OP_mEs : AIEBaseRegisterOperand<mEs>;
17+
def OP_mAguSrc : AIEBaseRegisterOperand<mAguSrc>;
18+
def OP_mQXsb : AIEBaseRegisterOperand<mQXsb>;
19+
def OP_mEhm : AIEBaseRegisterOperand<mEhm>;
20+
def OP_mLdaScl : AIEBaseRegisterOperand<mLdaScl>;
21+
def OP_mQQsm : AIEBaseRegisterOperand<mQQsm>;
22+
def OP_mWs : AIEBaseRegisterOperand<mWs>;
23+
def OP_mXw : AIEBaseRegisterOperand<mXw>;
24+
def OP_mAguDst : AIEBaseRegisterOperand<mAguDst>;
25+
def OP_mEXm : AIEBaseRegisterOperand<mEXm>;
26+
def OP_mQXsa : AIEBaseRegisterOperand<mQXsa>;
27+
def OP_mDm : AIEBaseRegisterOperand<mDm>;
28+
def OP_mQQss : AIEBaseRegisterOperand<mQQss>;
29+
def OP_mQXsm : AIEBaseRegisterOperand<mQXsm>;
30+
def OP_mShflBMDst : AIEBaseRegisterOperand<mShflBMDst>;
31+
def OP_mBMm : AIEBaseRegisterOperand<mBMm>;
32+
def OP_mMvBMXDst : AIEBaseRegisterOperand<mMvBMXDst>;
33+
def OP_mShflXDst : AIEBaseRegisterOperand<mShflXDst>;
34+
def OP_mMvSclDst : AIEBaseRegisterOperand<mMvSclDst>;
35+
def OP_mMcdXSrc : AIEBaseRegisterOperand<mMcdXSrc>;
36+
def OP_mEXn : AIEBaseRegisterOperand<mEXn>;
37+
def OP_mMvSclDstCg : AIEBaseRegisterOperand<mMvSclDstCg>;
38+
def OP_mSclMS : AIEBaseRegisterOperand<mSclMS>;
39+
def OP_mXn : AIEBaseRegisterOperand<mXn>;
40+
def OP_mBMSm : AIEBaseRegisterOperand<mBMSm>;
41+
def OP_mXv : AIEBaseRegisterOperand<mXv>;
42+
def OP_mWb : AIEBaseRegisterOperand<mWb>;
43+
def OP_mMvBMXSrc : AIEBaseRegisterOperand<mMvBMXSrc>;
44+
def OP_mAluCg : AIEBaseRegisterOperand<mAluCg>;
45+
def OP_mEXw : AIEBaseRegisterOperand<mEXw>;
46+
def OP_mXs : AIEBaseRegisterOperand<mXs>;
47+
def OP_mEXs : AIEBaseRegisterOperand<mEXs>;
48+
def OP_mCMs : AIEBaseRegisterOperand<mCMs>;
49+
def OP_mFifoHLReg : AIEBaseRegisterOperand<mFifoHLReg>;
50+
def OP_mSRm : AIEBaseRegisterOperand<mSRm>;
51+
def OP_mElm : AIEBaseRegisterOperand<mElm>;
52+
def OP_mQEXsw : AIEBaseRegisterOperand<mQEXsw>;
53+
def OP_mQQsa : AIEBaseRegisterOperand<mQQsa>;
54+
def OP_mEXv : AIEBaseRegisterOperand<mEXv>;
55+
def OP_mXa : AIEBaseRegisterOperand<mXa>;
56+
def OP_mWm : AIEBaseRegisterOperand<mWm>;
57+
def OP_mMvSclSrc : AIEBaseRegisterOperand<mMvSclSrc>;
58+
def OP_mQEXsa : AIEBaseRegisterOperand<mQEXsa>;
59+
def OP_mCRm : AIEBaseRegisterOperand<mCRm>;
60+
def OP_mSclSt : AIEBaseRegisterOperand<mSclSt>;
61+
def OP_mMcdBMSrc : AIEBaseRegisterOperand<mMcdBMSrc>;
62+
def OP_mQXsw : AIEBaseRegisterOperand<mQXsw>;
63+
def OP_mEXa : AIEBaseRegisterOperand<mEXa>;
64+
def OP_mQEXsb : AIEBaseRegisterOperand<mQEXsb>;
65+
def OP_mLdaCg : AIEBaseRegisterOperand<mLdaCg>;
66+
def OP_mFl2FxSrc_W : AIEBaseRegisterOperand<mFl2FxSrc_W>;
67+
def OP_mXb : AIEBaseRegisterOperand<mXb>;
68+
def OP_mBMs : AIEBaseRegisterOperand<mBMs>;
69+
def OP_mEXb : AIEBaseRegisterOperand<mEXb>;

‎llvm/lib/Target/AIE/AIE2RegOperandDef.td‎

Lines changed: 19 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -7,36 +7,32 @@
77
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
88
//
99
//===----------------------------------------------------------------------===//
10-
class AIE2RegisterOperand<RegisterClass c> : RegisterOperand<c> {
11-
let EncoderMethod = "get" # c # OpValue;
12-
let hasCompleteDecoder = false;
13-
}
14-
def OP_mDm : AIE2RegisterOperand<mDm>;
10+
def OP_mDm : AIEBaseRegisterOperand<mDm>;
1511
def OP_mMvSclDst_and_eR : RegisterOperand<eR> {
1612
let EncoderMethod = "getmMvSclDstOpValue";
1713
}
18-
def OP_mAluCg :AIE2RegisterOperand<mAluCg>;
19-
def OP_mMvSclDst :AIE2RegisterOperand<mMvSclDst>;
20-
def OP_mMvSclDstCg :AIE2RegisterOperand<mMvSclDstCg>;
21-
def OP_mMvSclSrc :AIE2RegisterOperand<mMvSclSrc>;
22-
def OP_mLdaScl :AIE2RegisterOperand<mLdaScl>;
23-
def OP_mSclSt :AIE2RegisterOperand<mSclSt>;
24-
def OP_mSclMS :AIE2RegisterOperand<mSclMS>;
25-
def OP_mLdaCg :AIE2RegisterOperand<mLdaCg>;
26-
def OP_mWm_1 :AIE2RegisterOperand<mWm_1>;
14+
def OP_mAluCg :AIEBaseRegisterOperand<mAluCg>;
15+
def OP_mMvSclDst :AIEBaseRegisterOperand<mMvSclDst>;
16+
def OP_mMvSclDstCg :AIEBaseRegisterOperand<mMvSclDstCg>;
17+
def OP_mMvSclSrc :AIEBaseRegisterOperand<mMvSclSrc>;
18+
def OP_mLdaScl :AIEBaseRegisterOperand<mLdaScl>;
19+
def OP_mSclSt :AIEBaseRegisterOperand<mSclSt>;
20+
def OP_mSclMS :AIEBaseRegisterOperand<mSclMS>;
21+
def OP_mLdaCg :AIEBaseRegisterOperand<mLdaCg>;
22+
def OP_mWm_1 :AIEBaseRegisterOperand<mWm_1>;
2723

2824
// VMOV Operands
29-
def OP_mMvAMWQSrc :AIE2RegisterOperand<mMvAMWQSrc>;
30-
def OP_mMvAMWQDst :AIE2RegisterOperand<mMvAMWQDst>;
31-
def OP_mMvBMXSrc :AIE2RegisterOperand<mMvBMXSrc>;
32-
def OP_mMvBMXDst :AIE2RegisterOperand<mMvBMXDst>;
33-
def OP_mMcdSrc :AIE2RegisterOperand<mMvBMXDst>;
34-
def OP_mScdDst :AIE2RegisterOperand<mMvBMXDst>;
25+
def OP_mMvAMWQSrc :AIEBaseRegisterOperand<mMvAMWQSrc>;
26+
def OP_mMvAMWQDst :AIEBaseRegisterOperand<mMvAMWQDst>;
27+
def OP_mMvBMXSrc :AIEBaseRegisterOperand<mMvBMXSrc>;
28+
def OP_mMvBMXDst :AIEBaseRegisterOperand<mMvBMXDst>;
29+
def OP_mMcdSrc :AIEBaseRegisterOperand<mMvBMXDst>;
30+
def OP_mScdDst :AIEBaseRegisterOperand<mMvBMXDst>;
3531

3632
// VSHUFFLE Operands
37-
def OP_mShflDst :AIE2RegisterOperand<mShflDst>;
33+
def OP_mShflDst :AIEBaseRegisterOperand<mShflDst>;
3834

39-
def OP_mRS4m :AIE2RegisterOperand<eRS4>;
35+
def OP_mRS4m :AIEBaseRegisterOperand<eRS4>;
4036

4137
// VLDB.SPARSE Operands
42-
def OP_mQXHLb :AIE2RegisterOperand<mQXHLb>;
38+
def OP_mQXHLb :AIEBaseRegisterOperand<mQXHLb>;
Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
//===-- AIEBaseRegisterInfo.td - Base Register Info for AIE -*- tablegen -*-===//
2+
//
3+
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
// (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
8+
//
9+
//===----------------------------------------------------------------------===//
10+
//
11+
// This file contains a generic utility class for AIE register classes
12+
//
13+
//===----------------------------------------------------------------------===//
14+
15+
// Base class for all AIE register classes across all targets
16+
// This centralizes common decoder properties that should be applied to all
17+
// register classes in the AIE targets.
18+
class AIEBaseRegisterClass<string namespace, list<ValueType> regTypes, int alignment,
19+
dag regList, RegAltNameIndex idx = NoRegAltName> :
20+
RegisterClass<namespace, regTypes, alignment, regList, idx> {
21+
// Enable decoding of zero-bit operands
22+
bit DecodeZeroBitOperand = true;
23+
24+
// Disable complete decoder for all register classes to avoid decoder
25+
// conflicts between instructions with overlapping encodings
26+
bit hasCompleteDecoder = false;
27+
}
28+
29+
// Base class for all AIE register operands across all targets
30+
// This centralizes common decoder properties for register operands.
31+
class AIEBaseRegisterOperand<RegisterClass c> : RegisterOperand<c> {
32+
// Set encoder method based on register class name
33+
let EncoderMethod = "get" # c # OpValue;
34+
35+
// Disable complete decoder for all register operands to avoid decoder
36+
// conflicts between instructions with overlapping encodings
37+
let hasCompleteDecoder = false;
38+
}
39+

‎llvm/lib/Target/AIE/aie1/AIE1InstrInfo.td‎

Lines changed: 25 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -93,48 +93,44 @@ def immfp32 : ImmLeaf<f32, [{return true;}] >;
9393
// code to encode registers correctly on a per-registerClass basis.
9494
// (Note that decoding in the disassembler is done on a
9595
// per-registerClass basis by default.)
96-
class AIERegisterOperand<RegisterClass c> : RegisterOperand<c> {
97-
let EncoderMethod = "get" # c # OpValue;
98-
let hasCompleteDecoder = false;
99-
}
10096

10197
// WARNING: These register classes contain registers of different
10298
// sizes! This case is not well handled in LLVM and can silently
10399
// cause miscompilations if a 20-bit (PTR) register is chosen to store
104100
// a value that doesn't fit! Codegen patterns should use the
105101
// more specialized *_GPR and *_PTR register classes below.
106-
def OP_mMvScl :AIERegisterOperand<mMvScl>;
107-
def OP_mSclSt :AIERegisterOperand<mSclSt>;
108-
def OP_mLdaScl :AIERegisterOperand<mLdaScl>;
102+
def OP_mMvScl :AIEBaseRegisterOperand<mMvScl>;
103+
def OP_mSclSt :AIEBaseRegisterOperand<mSclSt>;
104+
def OP_mLdaScl :AIEBaseRegisterOperand<mLdaScl>;
109105

110106
let EncoderMethod = "get" # mMvScl # OpValue in {
111-
def OP_mMvScl_GPR :AIERegisterOperand<mRCm>;
112-
def OP_mMvScl_PTR :AIERegisterOperand<PTRMODCSCB>;
107+
def OP_mMvScl_GPR :AIEBaseRegisterOperand<mRCm>;
108+
def OP_mMvScl_PTR :AIEBaseRegisterOperand<PTRMODCSCB>;
113109
}
114110
let EncoderMethod = "get" # mSclSt # OpValue in {
115-
def OP_mSclSt_GPR :AIERegisterOperand<mRCm>;
116-
def OP_mSclSt_PTR :AIERegisterOperand<mSclSt_PTR>;
117-
def OP_mSclSt_MOD :AIERegisterOperand<MOD>;
111+
def OP_mSclSt_GPR :AIEBaseRegisterOperand<mRCm>;
112+
def OP_mSclSt_PTR :AIEBaseRegisterOperand<mSclSt_PTR>;
113+
def OP_mSclSt_MOD :AIEBaseRegisterOperand<MOD>;
118114
}
119115
let EncoderMethod = "get" # mLdaScl # OpValue in {
120-
def OP_mLdaScl_GPR :AIERegisterOperand<mRCm>;
121-
def OP_mLdaScl_PTR :AIERegisterOperand<PTRMODCSCB>;
122-
def OP_mLdaScl_MOD :AIERegisterOperand<MOD>;
123-
}
124-
125-
def OP_mLdbScl :AIERegisterOperand<mLdbScl>;
126-
def OP_mAluCg12 :AIERegisterOperand<mAluCg12>;
127-
def OP_mMv0Cg20 :AIERegisterOperand<mMv0Cg20>;
128-
def OP_mRCm :AIERegisterOperand<mRCm>;
129-
def OP_mWAv :AIERegisterOperand<mWAv>;
130-
def OP_mWABv :AIERegisterOperand<mWABv>;
131-
def OP_mWABDv :AIERegisterOperand<mWABDv>;
132-
def OP_mWBDv :AIERegisterOperand<mWBDv>;
133-
def OP_mWCDv :AIERegisterOperand<mWCDv>;
134-
def OP_mXABv :AIERegisterOperand<mXABv>;
135-
def OP_mXCDv :AIERegisterOperand<mXCDv>;
116+
def OP_mLdaScl_GPR :AIEBaseRegisterOperand<mRCm>;
117+
def OP_mLdaScl_PTR :AIEBaseRegisterOperand<PTRMODCSCB>;
118+
def OP_mLdaScl_MOD :AIEBaseRegisterOperand<MOD>;
119+
}
120+
121+
def OP_mLdbScl :AIEBaseRegisterOperand<mLdbScl>;
122+
def OP_mAluCg12 :AIEBaseRegisterOperand<mAluCg12>;
123+
def OP_mMv0Cg20 :AIEBaseRegisterOperand<mMv0Cg20>;
124+
def OP_mRCm :AIEBaseRegisterOperand<mRCm>;
125+
def OP_mWAv :AIEBaseRegisterOperand<mWAv>;
126+
def OP_mWABv :AIEBaseRegisterOperand<mWABv>;
127+
def OP_mWABDv :AIEBaseRegisterOperand<mWABDv>;
128+
def OP_mWBDv :AIEBaseRegisterOperand<mWBDv>;
129+
def OP_mWCDv :AIEBaseRegisterOperand<mWCDv>;
130+
def OP_mXABv :AIEBaseRegisterOperand<mXABv>;
131+
def OP_mXCDv :AIEBaseRegisterOperand<mXCDv>;
136132
//mVn, mVs, mVm, mVa
137-
def OP_mVn :AIERegisterOperand<mVn>;
133+
def OP_mVn :AIEBaseRegisterOperand<mVn>;
138134

139135
// Extract least significant 20 bits from an immediate value.
140136
def LO20 : SDNodeXForm<imm, [{

‎llvm/lib/Target/AIE/aie1/AIE1RegisterInfo.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,8 @@
1212
// Declarations that describe the AIEngine register files
1313
//===----------------------------------------------------------------------===//
1414

15+
include "AIEBaseRegisterInfo.td"
16+
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let Namespace = "AIE" in {
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1719
class AIEReg<string n> : Register<n> {
@@ -201,19 +203,17 @@ let SubRegIndices = [sub_32_lo, sub_32_hi], CoveredBySubRegs = 1 in {
201203
// We have lots of different register classes, representing register
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// restrictions for different instructions
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class AIERegisterClass <int size, list<ValueType> regTypes, dag reglist, RegAltNameIndex idx = NoRegAltName> :
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RegisterClass<"AIE", regTypes, /*alignment*/size, reglist, idx> {
206+
AIEBaseRegisterClass<"AIE", regTypes, /*alignment*/size, reglist, idx> {
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dag Regs = reglist;
206-
let DecodeZeroBitOperand = true;
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let RegInfos = RegInfoByHwMode<
208209
[DefaultMode],
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[RegInfo</*size*/size, /*spill size*/size, /*spill alignment*/size>]>;
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let hasCompleteDecoder = false;
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}
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class AIEScalarRegisterClass <dag reglist, RegAltNameIndex idx = NoRegAltName> :
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AIERegisterClass<32, [v8i1, v16i1, i20, i32, f32], reglist, idx>;
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class AIEPointerRegisterClass <dag reglist, RegAltNameIndex idx = NoRegAltName> :
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RegisterClass<"AIE", [i20], /*alignment*/ 32, reglist, idx> {
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AIEBaseRegisterClass<"AIE", [i20], /*alignment*/ 32, reglist, idx> {
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dag Regs = reglist;
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let RegInfos = RegInfoByHwMode<
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[DefaultMode],

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