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A simple 16-bit CPU built in Logisim
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Theldus/MSW
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MSW is a 16-bit CPU, RISC, Unicycle, Harvard, built inLogisim.
It is designed to be as simple as possible, so it is not cumbersome to understand the entire circuit, as well as the instruction set and the assembler. It is primarily suitable for students of Computer Architecture. Because of this, it has no pipeline, branch prediction, cache, among other features.
MSW Overview
Inspired by the Intel 8086 and MIPS, but much simpler, its instruction set has 16 instructions and similar registers with Intel. Its general architecture looks like a MIPS unicycle.
It is divided into 4 parts:
- ALU: Arithmetic Logic Unit
- UControl: Unity Control, responsible for creating control flags throughout the CPU, according to the instruction currently running.
- BRegs: Register Bank.
- CPU: Final module, containing the full assembly of the other modules.
The MSW's instructions follows the format below:
OpCode R1 R2 Imm/-------\ /-\ /-\ /------------------\ - Immediate instructions. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0and
OpCode R1 R2 Constant/-------\ /-\ /-\ /------------------\ - Only registers. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1Supports 16 instructions and 4 registers: AX, BX, CX and DX.* Due the use of 0x00FF to identify Register-only instructions, youshouldn't use 255 as immediate value.
The following table illustrates all instructions:
| Op Code | Instruction | Behavior |
|---|---|---|
| 0 | OR REGDest,REGSource/Imm | REGDest <- REGDest | REGSource |
| 1 | NOT REGDest | REGDest <- ~REGDest |
| 2 | AND REGDest,REGSource/Imm | REGDest <- REGDest & REGOri |
| 3 | XOR REGDest,REGSource/Imm | REGDest <- REGDest ^ REGOri |
| 4 | ADD REGDest,REGSource/Imm | REGDest <- REGDest + REGOri |
| 5 | SUB REGDest,REGSource/Imm | REGDest <- REGDest - REGOri |
| 6 | MULT REGDest,REGSource/Imm | REGDest <- REGDest * REGOri |
| 7 | DIV REGDest,REGSource/Imm | REGDest <- REGDest / REGOri |
| 8 | MOV REGDest, REGSource | REGDest <- REGSource |
| 9 | MOV REGDest, Imm | REGDest <- Imm |
| 10 | LOAD REGDest, REGSource | REGDest <- MEM[REGSource] |
| 11 | STORE REGDest, REGSource | MEM[REGDest] <- REGSource |
| 12 | JMPZ REGDest/Label | JuMP if Zero |
| 13 | JMPN REGDest/Label | JuMP if Negative |
| 14 | JMPP REGDest/Label | JuMP if Positive |
| 15 | HALT | Halts CPU |
In order to avoid programming directly in binary, MSW also comes with an Assembler, that takes a file as input and generates a hex file ready to run. A code like below can be perfectly executed on the CPU:
####################FibonAsm, ^.^######################Calculation of Fibonaccimov ax,1 #ixor bx,bx #jxor cx,cx #<-- memmov dx,14 #counterfibo:add ax,bx #i=i+jstore cx,ax #mem[0] = imov ax,bx #i=jload bx,cx #j=mem[0]sub dx,1 #count=count-1jmpp fibohalt#Result in bxThe assembler is case insensitive for instruction names, supports labels and comments.
To run the generated program (.hex), just load it to the leftmost memory and activate the clock.Here is a video of the CPUin operation (Portuguese).
This is my first CPU and I believe there are some design issues in both the CPU and the Assembler (not bugs, just the wayI developed).
So I don't intend to go far with it, there are still some things I want to add such as stack and I/O instructions, butthe ideal would be a re-work on a new CPU, very different from this first, starting with microcode addition eg.
That's it, if you have questions, suggestions or want to contribute, feel free to ask me, I would love hear from you.