Commit01a6fe7

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Merge branch 'SetBit'

2 parentscab1760 +58fca82 commit01a6fe7Copy full SHA for 01a6fe7

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Lines changed: 4 additions & 4 deletions

Original file line number	Diff line number	Diff line change
`@@ -1,21 +1,21 @@`
`1`	`1`	`import{setBit}from'../SetBit'`
`2`	`2`
`3`		`-test('should setbitat the given bit Position',()=>{`
	`3`	`+test('Setbitnumber 0 in 1:',()=>{`
`4`	`4`	`constsetBitPos=setBit(1,0)`
`5`	`5`	`expect(setBitPos).toBe(1)`
`6`	`6`	`})`
`7`	`7`
`8`		`-test('should setbitat the given bit Position',()=>{`
	`8`	`+test('Setbitnumber 0 in 1:',()=>{`
`9`	`9`	`constsetBitPos=setBit(1,0)`
`10`	`10`	`expect(setBitPos).toBe(1)`
`11`	`11`	`})`
`12`	`12`
`13`		`-test('should setbitat the given bit Position',()=>{`
	`13`	`+test('Setbitnumber 0 in 1:',()=>{`
`14`	`14`	`constsetBitPos=setBit(10,1)`
`15`	`15`	`expect(setBitPos).toBe(10)`
`16`	`16`	`})`
`17`	`17`
`18`		`-test('should setbitat the given bit Position',()=>{`
	`18`	`+test('Setbitnumber 0 in 1:',()=>{`
`19`	`19`	`constsetBitPos=setBit(10,2)`
`20`	`20`	`expect(setBitPos).toBe(14)`
`21`	`21`	`})`

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