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A university project about using FPGAs.

• A Digilent Basys3 board. (Other FPGAs might work but need adjusted code.)
• A composite adapter (TODO: schematics)
• Install LiteX:https://github.com/enjoy-digital/litex/wiki/Installation
• Install Rust:https://rustup.rs
  • Install RISC-V toolchain:$ rustup target add riscv32imac-unknown-none-elf
  • Install LLVM tools:$ rustup component add llvm-tools
  • Install cargo binutils:$ cargo install cargo-binutils

To just compile the binary for the internal risc-v cpu you can runcargo xtask build [--release]

To synthesize the SoC you have to either add the Vivado folder to yourPATH or to theLITEX_ENV_VIVADO env variable.Then you can simply run:cargo xtask synthesize --release [--terminal-uart].(When synthesizing, --release because the binary file needs to be as small as possible)