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SpinalHDL(1.12.2/1.12.3/1.13.0) cannot run large projects on computers with less than or equal to 16GB of memory

Status: Open.

#1817 In SpinalHDL/SpinalHDL;

·HaroldZ32 openedon Sep 29, 2025

UFix.fractionalPart broken

Status: Open.

#1814 In SpinalHDL/SpinalHDL;

·louiecaulfield openedon Sep 24, 2025

Upgrade mill support to newer version

Status: Open.

#1803 In SpinalHDL/SpinalHDL;

·KireinaHoro openedon Sep 11, 2025

Spinal Hanging when running simulation with IVerilog

Status: Open.

#1789 In SpinalHDL/SpinalHDL;

·Ofthemasses openedon Aug 18, 2025

TimingExtractor with CC queue

Status: Open.

#1782 In SpinalHDL/SpinalHDL;

·oletf openedon Aug 11, 2025

ASIC synthesis issues for Mem with multiple write ports

Status: Open.

#1763 In SpinalHDL/SpinalHDL;

·7FM openedon Jul 9, 2025

The PSL support on Windows do not follow the assume directive.

Status: Open.

#1762 In SpinalHDL/SpinalHDL;

·Readon openedon Jul 8, 2025

When I use iverilog, can I avoid importing __zz* signal into fst waveform?

Status: Open.

#1755 In SpinalHDL/SpinalHDL;

·buloruabutata openedon Jul 4, 2025

Impossibility to add attributes to clock wire

Status: Open.

#1750 In SpinalHDL/SpinalHDL;

·FrancescoCiraolo openedon Jun 25, 2025

Problem with Mixed-width RAM

Status: Open.

#1742 In SpinalHDL/SpinalHDL;

·XUEHongjia openedon Jun 4, 2025

Can ClockDomain.clock.setName() be local ?

Status: Open.

#1741 In SpinalHDL/SpinalHDL;

·balanx openedon May 30, 2025

ClockDomain.current made CLOCK CROSSING VIOLATION

Status: Open.

#1739 In SpinalHDL/SpinalHDL;

·balanx openedon May 27, 2025