Switch the default mes to uni mes for gfx v12.V2: remove uni_mes set for gfx v11.Signed-off-by: Likun Gao <Likun.Gao@amd.com>Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>

Enable mmhub and athub cg on gc 12.0.0Signed-off-by: Likun Gao <Likun.Gao@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Enable GFXOFF for GC v12.0.0.Signed-off-by: Likun Gao <Likun.Gao@amd.com>Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>

add pp_dpm_dcefclk for smu 14.0.2/3Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>Reviewed-by: Jack Gui <Jack.Gui@amd.com>

use mc address for wptr in add queue packetSigned-off-by: Frank Min <Frank.Min@amd.com>Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>Acked-by: Alex Deucher <alexander.deucher@amd.com>

gfx12 query video mem channel/type/width from umc_info of atom list, sofix it accordingly.Signed-off-by: Frank Min <Frank.Min@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Acked-by: Alex Deucher <alexander.deucher@amd.com>

disable gpo temprarily since it is not ready in fwSigned-off-by: Kenneth Feng <kenneth.feng@amd.com>Reviewed-by: Jack Gui <Jack.Gui@amd.com>

create a new helper function to avoid compiler 'side-effect'check about RAS_EVENT_LOG() macro.Signed-off-by: Yang Wang <kevinyang.wang@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

gpu_id needs to be unique for user space to identify GPUs via KFDinterface. In the current implementation there is a very smallprobability of having non unique gpu_ids.v2: Add check to confirm if gpu_id is unique. If not unique, find one    Changed commit header to reflect the abovev3: Use crc16 as suggested-by: Lijo Lazar <lijo.lazar@amd.com>    Ensure that gpu_id != 0Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>

Fix up parameter descriptions.Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

To catch GPU mapping of system memory, TTM_PL_TT and AMDGPU_PL_PREEMPTmust be checked.Fixes: 7c06cc729edc ("drm/amdkfd: mark GFX12 system and peer GPU memory mappings as MTYPE_NC")Signed-off-by: Sreekant Somasekharan <sreekant.somasekharan@amd.com>Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>

Fix up parameter descriptions.Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

GFX1201 was missed in the commit below. Adding it in.Fixes: 7c06cc729edc ("drm/amdkfd: mark GFX12 system and peer GPU memory mappings as MTYPE_NC")Signed-off-by: Sreekant Somasekharan <sreekant.somasekharan@amd.com>Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

add module parameter for jpeg. this is a temporary workaround for jpeg unit test failon vcn 5.0 now. will be removed later.Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>

support pp_dpm_pcie on smu v14.0.2/3Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>Reviewed-by: Jack Gui <Jack.Gui@amd.com>

When user sets an interval less than what driver can handle, soft lockup arises.To clear this soft lockup with adding a schedule before trigger a new host trap.[ 2896.405488] watchdog: BUG: soft lockup - CPU#22 stuck for 26s! [pcs_130:38057][ 2896.405676] Supported: No, Unsupported modules are loaded[ 2896.405678] CPU: 22 PID: 38057 Comm: pcs_130 Kdump: loaded Tainted: G           OE  X  N 5.14.21-150500.55.59-defaultROCm#1 SLE15-SP5 3a8569df5696e57cdcb648c7e890af33bdc23f85[ 2896.405683] Hardware name: Dell Inc. PowerEdge R7525/0590KW, BIOS 2.6.6 01/13/2022[ 2896.405684] RIP: 0010:amdgpu_device_rreg.part.42+0x57/0x1d0 [amdgpu][ 2896.405978] Code: 6f 4c 9c 00 4c 8b 83 b8 08 00 00 4d 01 e0 85 c9 74 15 65 48 8b 04 25 00 1c 02 00 3b 88 b8 09 00 00 0f 85 52 01 00 00 41 8b 28 <8b> 05 43 4c 9c 00 85 c0 74 56 65 48 8b 14 25 00 1c 02 00 39 82 b8[ 2896.405981] RSP: 0018:ffffb7a6ecc33e30 EFLAGS: 00000246[ 2896.405984] RAX: ffff949389f18000 RBX: ffff94d3d1100000 RCX: 00000000000094a9[ 2896.405985] RDX: 0000000000000000 RSI: 0000000000002376 RDI: ffff94d3d1100000[ 2896.405987] RBP: 0000000000000000 R08: ffffb7a6e2b88dd8 R09: ffff94d30e3b1f14[ 2896.405989] R10: ffffb7a6c0427d88 R11: ffffb7a6ecc33c80 R12: 0000000000008dd8[ 2896.405990] R13: 0000000000002376 R14: ffff94d30e3b1f14 R15: ffff94d3d1100000[ 2896.405992] FS:  0000000000000000(0000) GS:ffff9512ff580000(0000) knlGS:0000000000000000[ 2896.405994] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033[ 2896.405996] CR2: 00007f5b2b732000 CR3: 0000006a1ee10003 CR4: 0000000000770ee0[ 2896.405998] PKRU: 55555554[ 2896.405999] Call Trace:[ 2896.406004]  <TASK>[ 2896.406007]  kgd_gfx_v9_trigger_pc_sample_trap+0x1d6/0x4f0 [amdgpu 75bb93fc913928fc00917a1c71d5c2dca258175d]Signed-off-by: James Zhu <James.Zhu@amd.com>Tested-by: Vladimir Indic <Vladimir.Indic@amd.com>Reviewed-by: Vladimir Indic <Vladimir.Indic@amd.com>

When host trap pc sampling is activted. Since Command bus from SPI/SQGto SQ may have some conflict with SQ internal clock gating, when we havemany host trap command it will trigger qcm fence timeout.Signed-off-by: James Zhu <James.Zhu@amd.com>Tested-by: Vladimir Indic <Vladimir.Indic@amd.com>Reviewed-by: Vladimir Indic <Vladimir.Indic@amd.com>

Signed-off-by: Asher Song <Asher.Song@amd.com>

Signed-off-by: Asher Song <Asher.Song@amd.com>

is_smca_umc_v2 function never occurs in upstream kernel, macro HAVE_SMCA_UMC_V2is undefined all the time, which cause MCE notifications is nothandled on MI200 A+A platform. So we drop macro HAVE_SMCA_UMC_V2.On the other hand, on Centos 7.9, SMCA_UMC_V2 is not defined inarch/x86/include/asm/mce.h, we don't care umc_v2 errornotification on centos 7.9.Signed-off-by: Asher Song <Asher.Song@amd.com>Reviewed-by:  Flora Cui <flora.cui@amd.com>Reviewed-by:  Bob Zhou <bob.zhou@amd.com>

When redefining HAVE_SMCA_UMC_V2, the fake function smca_get_bank_typeis called by amdgpu_bad_page_notifier. However origin fake function cannot be referenced when making intree build as it defined in amdkclmodules.So we make a macro for the fake function in backport/kcl_mce.hSigned-off-by: Asher Song <Asher.Song@amd.com>Reviewed-by:  Flora Cui <flora.cui@amd.com>Reviewed-by:  Bob Zhou <bob.zhou@amd.com>

There is a typo in patch drm/amdkcl: fake smca_get_bank_type, fix itSigned-off-by: Asher Song <Asher.Song@amd.com>Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>

The parameters segment_width and last_segment_width are used to controlthe configuration of the Output Plane Processor (OPP), specifically thewidth of each segment that the display is divided into and the width ofthe last segmentFixes the below with gcc W=1:drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Function parameter or struct member 'segment_width' not described in 'optc35_set_odm_combine'drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Function parameter or struct member 'last_segment_width' not described in 'optc35_set_odm_combine'drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Excess function parameter 'timing' description in 'optc35_set_odm_combine'Cc: Tom Chung <chiahsuan.chung@amd.com>Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Cc: Roman Li <roman.li@amd.com>Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>

Align with new port same as smu 13.x.Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>Reviewed-by: Jack Gui <Jack.Gui@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Update the capabilities for supporting 8k encoding.Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>Acked-by: Alex Deucher <alexander.deucher@amd.com>Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>

The following commit updated gmc->noretry from 0 to 1 for GC HW IP9.3.0:    commit5f3854f ("drm/amdgpu: add more cases to noretry=1")This causes the device to hang when a page fault occurs, until thedevice is rebooted. Instead, revert back to gmc->noretry=0 so the deviceis still responsive.Fixes:5f3854f ("drm/amdgpu: add more cases to noretry=1")Signed-off-by: Tim Van Patten <timvp@google.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

./drivers/gpu/drm/amd/amdgpu/amdgpu.h: amdgpu_umsch_mm.h is included more than once.Reported-by: Abaci Robot <abaci@linux.alibaba.com>Closes:https://bugzilla.openanolis.cn/show_bug.cgi?id=9063Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

…ing_set_wptrThis commit removes a duplicate check for *is_queue_unmap in thesdma_v7_0_ring_set_wptr function. The check at line 171 was considereddead code because at this point in the code, we already know that*is_queue_unmap is false due to the check at line 161.By removing this unnecessary check, improves the readability of thecodeFixes the below:drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c:171 sdma_v7_0_ring_set_wptr()warn: duplicate check '*is_queue_unmap' (previous on line 161)drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c    140 static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring)    141 {    142         struct amdgpu_device *adev = ring->adev;    143         uint32_t *wptr_saved;    144         uint32_t *is_queue_unmap;    145         uint64_t aggregated_db_index;    146         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;    147    148         DRM_DEBUG("Setting write pointer\n");    149    150         if (ring->is_mes_queue) {    151                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);    152                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +                        ^^^^^^^^^^^^^^^^ Set here    153                                               sizeof(uint32_t));    154                 aggregated_db_index =    155                         amdgpu_mes_get_aggregated_doorbell_index(adev,    156                                                          ring->hw_prio);    157    158                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,    159                              ring->wptr << 2);    160                 *wptr_saved = ring->wptr << 2;    161                 if (*is_queue_unmap) {                            ^^^^^^^^^^^^^^^ Checked here    162                         WDOORBELL64(aggregated_db_index, ring->wptr << 2);    163                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",    164                                         ring->doorbell_index, ring->wptr << 2);    165                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);    166                 } else {    167                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",    168                                         ring->doorbell_index, ring->wptr << 2);    169                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);    170--> 171                         if (*is_queue_unmap)                                    ^^^^^^^^^^^^^^^ This is dead code.  We know it's false.    172                                 WDOORBELL64(aggregated_db_index,    173                                             ring->wptr << 2);    174                 }    175         } else {    176                 if (ring->use_doorbell) {    177                         DRM_DEBUG("Using doorbell -- "    178                                   "wptr_offs == 0x%08x "Fixes: 6d9c711786e6 ("drm/amdgpu: Add sdma v7_0 ip block support (v7)")Cc: Likun Gao <Likun.Gao@amd.com>Cc: Hawking Zhang <Hawking.Zhang@amd.com>Cc: Christian König <christian.koenig@amd.com>Cc: Alex Deucher <alexander.deucher@amd.com>Reported-by: Dan Carpenter <dan.carpenter@linaro.org>Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>Reviewed-by: Likun Gao <Likun.Gao@amd.com>Reviewed-by: Asad Kamal <asad.kamal@amd.com>

modify the lock type to 'spinlock' to avoid schedule issuein interrupt context.Signed-off-by: Yang Wang <kevinyang.wang@amd.com>Reviewed-by: Tao Zhou <tao.zhou1@amd.com>

Add support to set/get information about different DPM policies. Thesupport is only available on SOCs which use swsmu architecture.A DPM policy type may be defined with different levels. For example, apolicy may be defined to select Pstate preference and then later apstate preference may be chosen.Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>Acked-by: Alex Deucher <alexander.deucher@amd.com>Reviewed-by: Asad Kamal <asad.kamal@amd.com>

…rarilynot for upstream.-v2: fix typo-v3: rename kfd_ioctl_pc_sample_args "reserved" to "version"Signed-off-by: James Zhu <James.Zhu@amd.com>Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>Reviewed-by: Vladimir Indic <Vladimir.Indic@amd.com>Tested-by: Vladimir Indic <Vladimir.Indic@amd.com>

This reverts commit6ac6a32.The fixed issue has disappeared, so revert the workaround.Signed-off-by: Bob Zhou <bob.zhou@amd.com>Reviewed-by: Jingwen Chen <Jingwen.Chen2@amd.com>

This reverts commit4ff45ec.The fixed issue has disappeared, so revert the workaround.Signed-off-by: Bob Zhou <bob.zhou@amd.com>Reviewed-by: Jingwen Chen <Jingwen.Chen2@amd.com>

We send back the ready to reset message before we stop anything. This iswrong. Move it to when we are actually ready for the FLR to happen.In the current state since we take tens of seconds to stop everything,it is very likely that host would give up waiting and reset the GPUbefore we send ready, so it would be the same as before. But this getsrid of the hack with reset_domain locking and also let us tell how slowready to reset actually is from the host. The ready to reset speed canbe improved later.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Acked-by: Christian König <christian.koenig@amd.com>Reviewed-by: Emily Deng <Emily.Deng@amd.com>

…dapterSigned-off-by: Vignesh Chander <Vignesh.Chander@amd.com>Reviewed-by: Zhigang Luo <Zhigang.Luo@amd.com>

For RAS error scenario, VF guest driver will check mailboxand set fed flag to avoid unnecessary HW accesses.additionally, poll for reset completion message firstto avoid accidentally spamming multiple reset requests to host.v2: add another mailbox check for handling case where kfd detectstimeout firstv3: set host_flr bit and use wait_for_resetSigned-off-by: Vignesh Chander <Vignesh.Chander@amd.com>Reviewed-by: Zhigang Luo <Zhigang.Luo@amd.com>

Flag "mes.ring.shced.ready" will be set as true after mes hw init and setas false when mes hw fini to avoid duplicate initialization. But hw finiwill not be called when function level reset, which will cause mes hwinit be skipped during FLR, which will leads to mapping legacy queuefail. Set this flag as false when post reset will fix this issue.Signed-off-by: Lin.Cao <lincao12@amd.com>Acked-by: Alex Deucher <alexander.deucher@amd.com>

Accessing registers via host is missing the check for skip_hw_access andthe lockdep check that comes with it.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Reviewed-by: Christian König <christian.koenig@amd.com>

is_hws_hang and is_resetting serves pretty much the same purpose andthey all duplicates the work of the reset_domain lock, just check thatdirectly instead. This also eliminate a few bugs listed below and getrid of dqm->ops.pre_reset.kfd_hws_hang did not need to avoid scheduling another reset. If theon-going reset decided to skip GPU reset we have a bad time, otherwisethe extra reset will get cancelled anyway.remove_queue_mes forgot to check is_resetting flag compared to thepre-MES path unmap_queue_cpsch, so it did not block hw access duringreset correctly.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>

At this point the gart is not set up, there's no point to invalidate tlbhere and it could even be harmful.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Reviewed-by: Christian König <christian.koenig@amd.com>

When amdgpu_gart_invalidate_tlb helper is introduced this part was leftout of the conversion. Avoid the code duplication here.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Reviewed-by: Christian König <christian.koenig@amd.com>

Which method is used to flush tlb does not depend on whether a reset isin progress or not. We should skip flush altogether if the GPU will getreset. So put both path under reset_domain read lock.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Reviewed-by: Christian König <christian.koenig@amd.com>CC: stable@vger.kernel.org

We need to take the reset domain lock before flush hdp. We can't put thelock inside amdgpu_device_flush_hdp itself because it is used duringreset where we already take the write side lock.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Reviewed-by: Christian König <christian.koenig@amd.com>

We need to take the reset domain lock before talking to MES. While inthis case we can take the lock inside the mes helper. We can't do so formost other mes helpers since they are used during reset. So forconsistency sake we add the lock here.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>

Here since we are in reset and takes the reset_domain write side lockalready. We can't use the flush tlb helper which tries to take the readside.Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>Reviewed-by: Christian König <christian.koenig@amd.com>

This reverts commitd409c20.The commit is a partial revert that left things broken, also this wasnever ported back to drm-next.This revert is needed by patch serieshttps://gerrit-git.amd.com/c/brahma/ec/linux/+/1068977

Add support to tune phase detect parameters.Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Add debugfs nodes for enabling/disabling and tuning parameters used inphase detect.Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Add support for enabling phase detect and tuning params for SMUv13.0.6SOCs.Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Phase detect controls are only available for SMUv13.0.6 dGPUs. Createcontrol object only on those.Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

…or Linux kernel >= 6.8.0-44