Commit76c0ce8

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Revert "drm/amd/display: Only use ODM2:1 policy for high pixel rate displays"

This reverts commit8df9afa.Reviwed-by: Feifei Xu <feifxu@amd.com>Signed-off-by: Hongkun Zhang <hongkun.zhang@amd.com>

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Original file line number	Diff line number	Diff line change
`@@ -1915,7 +1915,6 @@ int dcn32_populate_dml_pipes_from_context(`
`1915`	`1915`	`context->stream_status[0].plane_count <=1&&`
`1916`	`1916`	`!dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal)&&`
`1917`	`1917`	`is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream)&&`
`1918`		`-pipe->stream->timing.pix_clk_100hz*100>DCN3_2_VMIN_DISPCLK_HZ&&`
`1919`	`1918`	`dc->debug.enable_single_display_2to1_odm_policy) {`
`1920`	`1919`	`pipes[pipe_cnt].pipe.dest.odm_combine_policy=dm_odm_combine_policy_2to1;`
`1921`	`1920`	`}`

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Original file line number	Diff line number	Diff line change
`@@ -37,7 +37,6 @@`
`37`	`37`	`#defineDCN3_2_MBLK_WIDTH 128`
`38`	`38`	`#defineDCN3_2_MBLK_HEIGHT_4BPE 128`
`39`	`39`	`#defineDCN3_2_MBLK_HEIGHT_8BPE 64`
`40`		`-#defineDCN3_2_VMIN_DISPCLK_HZ 717000000`
`41`	`40`
`42`	`41`	`#defineTO_DCN32_RES_POOL(pool)\`
`43`	`42`	`container_of(pool, struct dcn32_resource_pool, base)`

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