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Standard Cell Library based Memory Compiler using DFF/Latch cells.

Seethis document.

* Silicon proven does not imply that you should use it without whole-system,timing-annotated simulation to make sure that it works for your circuit.

There may be design-specific complications that may render DFFRAM (and indeedthe entire chip) unusable. Proceed with caution.

The objective of this project is to develop a DFF/Latch-based RAM, Register Fileand Cache custom compilation flow that utilizes standard cell librariesfollowing a standard ASIC (Application Specific Integrated Circuit)implementation approach. Different views (HDL netlist, HDL functional models,LEF, GDS, Timing, …) are all generated for a given size configuration.

The layout targets highly compact designs (85%+) as the cells are placed on thefloor plan using a custom placer. Moreover, the custom placer ensures that therouting will be relatively simple. Currently, the compiler uses OpenROAD routersto route the macros with great success.

The Compiler relies on basic building blocks to construct the layout ofdifferent RAM/RF/Cache configurations. Checkthe compiler documentation for more info. The following shows how a32x32 memory (DFF based) is constructed.

The generated layouts by the DFFRAM compilers for RAM32 as well as its buildingblocks are as follows:

• First, a byte, which is just 8 bits placed together...

• Put four of those side by side, and you get a 32-bit word...

• Stack eight of those for an 8 word bank of RAM...

• And stack 4 of these 8 words for a kilobit of RAM!

• We can keep going, but these images aren't getting any smaller. As a bonusthough, here is 64 kilobits:

That stuff you see on the right of each image? It's clock gates, decoders andthe like. Don't worry about it.

Currently, the can compiler generate the layout of the following configurations:

We currently do not recommend the use of 1RW1R. See this discussion for moreinfo:

#198

• RAM
  • 32 words with byte write enable (1RW and 1RW1R).
  • 128 words with byte write enable (1RW and 1RW1R).
  • 256 words with byte write enable (1RW and 1RW1R).
  • 512 words with byte write enable (1RW and 1RW1R).
  • 1024 words with byte write enable (1RW and 1RW1R).
  • 2048 words with byte write enable (1RW and 1RW1R).
• Register File
  • 32 x 32-bit words (2R1W)

TheOpenLane/ folder will contain good known OpenLaneconfigurations to build DFFRAM different macros.

• .github contains files for GitHub actions.
• docs/ contains documentation (😮)
• rtl/ contains RTL RAM file generators for benchmarking and comparisonpurposes.
• platforms/ contains PDK-specific files:
  • <pdk-name>/
    • <scl-name>/
      • _building_blocks/ contains a hierarchy of building blocks supported bythe compiler.
• placeram/ is the custom placer Python module.
• scripts/ has assisting scripts used by the flow.
• dffram.py is the compilation flow going from building blocks to LVS.

The following table compares the areas and bit densities of RAM macros generatedusing different means.

¹ All support 32-bit word reads and 1, 2, and 4 byteswrites.
² Values are based on the original layout produced by thecompiler. OpenRAM macros are typically wrapped to be useful w/ automated PnRASIC flows.

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