The simplest kind of constraint is a string full of letters, each ofwhich describes one kind of operand that is permitted. Here arethe letters that are allowed:
Whitespace characters are ignored and can be inserted at any positionexcept the first. This enables each alternative for different operands tobe visually aligned in the machine description even if they have differentnumber of constraints and modifiers.
A memory operand is allowed, with any kind of address that the machinesupports in general.Note that the letter used for the general memory constraint can bere-defined by a back end using theTARGET_MEM_CONSTRAINT macro.
A memory operand is allowed, but only if the address isoffsettable. This means that adding a small integer (actually,the width in bytes of the operand, as determined by its machine mode)may be added to the address and the result is also a valid memoryaddress.
For example, an address which is constant is offsettable; so is anaddress that is the sum of a register and a constant (as long as aslightly larger constant is also within the range of address-offsetssupported by the machine); but an autoincrement or autodecrementaddress is not offsettable. More complicated indirect/indexedaddresses may or may not be offsettable depending on the otheraddressing modes that the machine supports.
Note that in an output operand which can be matched by anotheroperand, the constraint letter ‘o’ is valid only when accompaniedby both ‘<’ (if the target machine has predecrement addressing)and ‘>’ (if the target machine has preincrement addressing).
A memory operand that is not offsettable. In other words, anything thatwould fit the ‘m’ constraint but not the ‘o’ constraint.
A memory operand with autodecrement addressing (either predecrement orpostdecrement) is allowed. In inlineasm this constraint is onlyallowed if the operand is used exactly once in an instruction that canhandle the side effects. Not using an operand with ‘<’ in constraintstring in the inlineasm pattern at all or using it in multipleinstructions isn’t valid, because the side effects wouldn’t be performedor would be performed more than once. Furthermore, on some targetsthe operand with ‘<’ in constraint string must be accompanied byspecial instruction suffixes like%U0 instruction suffix on PowerPCor%P0 on IA-64.
A memory operand with autoincrement addressing (either preincrement orpostincrement) is allowed. In inlineasm the same restrictionsas for ‘<’ apply.
A register operand is allowed provided that it is in a generalregister.
An operand is bound to hard register ‘r’ which may be any general,floating-point, or vector register except a fixed register like a stack pointerregister. The set of fixed registers is target dependent.
An immediate integer operand (one with constant value) is allowed.This includes symbolic constants whose values will be known only atassembly time or later.
An immediate integer operand with a known numeric value is allowed.Many systems cannot support assembly-time constants for operands lessthan a word wide. Constraints for these operands should use ‘n’rather than ‘i’.
Other letters in the range ‘I’ through ‘P’ may be defined ina machine-dependent fashion to permit immediate integer operands withexplicit integer values in specified ranges. For example, on the68000, ‘I’ is defined to stand for the range of values 1 to 8.This is the range permitted as a shift count in the shiftinstructions.
An immediate floating operand (expression codeconst_double) isallowed, but only if the target floating point format is the same asthat of the host machine (on which the compiler is running).
An immediate floating operand (expression codeconst_double orconst_vector) is allowed.
‘G’ and ‘H’ may be defined in a machine-dependent fashion topermit immediate floating operands in particular ranges of values.
An immediate integer operand whose value is not an explicit integer isallowed.
This might appear strange; if an insn allows a constant operand with avalue not known at compile time, it certainly must allow any knownvalue. So why use ‘s’ instead of ‘i’? Sometimes it allowsbetter code to be generated.
For example, on the 68000 in a fullword instruction it is possible touse an immediate operand; but if the immediate value is between −128and 127, better code results from loading the value into a register andusing the register. This is because the load into the register can bedone with a ‘moveq’ instruction. We arrange for this to happenby defining the letter ‘K’ to mean “any integer outside therange −128 to 127”, and then specifying ‘Ks’ in the operandconstraints.
Any register, memory or immediate integer operand is allowed, except forregisters that are not general registers.
Any operand whatsoever is allowed, even if it does not satisfygeneral_operand. This is normally used in the constraint ofamatch_scratch when certain alternatives will not actuallyrequire a scratch register.
An operand that matches the specified operand number is allowed. If adigit is used together with letters within the same alternative, thedigit should come last.
This number is allowed to be more than a single digit. If multipledigits are encountered consecutively, they are interpreted as a singledecimal integer. There is scant chance for ambiguity, since to-dateit has never been desirable that ‘10’ be interpreted as matchingeither operand 1or operand 0. Should this be desired, onecan use multiple alternatives instead.
This is called amatching constraint and what it really means isthat the assembler has only a single operand that fills two rolesconsidered separate in the RTL insn. For example, an add insn has twoinput operands and one output operand in the RTL, but on most CISCmachines an add instruction really has only two operands, one of them aninput-output operand:
addl #35,r12
Matching constraints are used in these circumstances.More precisely, the two operands that match must include one input-onlyoperand and one output-only operand. Moreover, the digit must be asmaller number than the number of the operand that uses it in theconstraint.
For operands to match in a particular case usually means that theyare identical-looking RTL expressions. But in a few special casesspecific kinds of dissimilarity are allowed. For example,*xas an input operand will match*x++ as an output operand.For proper results in such cases, the output template should alwaysuse the output-operand’s number when printing the operand.
An operand that is a valid memory address is allowed. This isfor “load address” and “push address” instructions.
‘p’ in the constraint must be accompanied byaddress_operandas the predicate in thematch_operand. This predicate interpretsthe mode specified in thematch_operand as the mode of the memoryreference for which the address would be valid.
This constraint, allowed only in input operands, says the inlineasmpattern defines specific function or variable symbol. The constraintshouldn’t be mixed with other constraints on the same operand andthe operand should be address of a function or non-automatic variable.Best used with the ‘cc’ modifier when printing the operand, so thateven in position independent code it prints as a label.
void foo (void);asm (".globl %cc0; %cc0: ret" : : ":" (foo));Other letters can be defined in machine-dependent fashion to stand forparticular classes of registers or other arbitrary operand types.‘d’, ‘a’ and ‘f’ are defined on the 68000/68020 to standfor data, address and floating point registers.
In order to have valid assembler code, each operand must satisfyits constraint. But a failure to do so does not prevent the patternfrom applying to an insn. Instead, it directs the compiler to modifythe code so that the constraint will be satisfied. Usually this isdone by copying an operand into a register.
Contrast, therefore, the two instruction patterns that follow:
(define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (plus:SI (match_dup 0) (match_operand:SI 1 "general_operand" "r")))] "" "…")
which has two operands, one of which must appear in two places, and
(define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (plus:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "r")))] "" "…")
which has three operands, two of which are required by a constraint to beidentical. If we are considering an insn of the form
(insnnprevnext (set (reg:SI 3) (plus:SI (reg:SI 6) (reg:SI 109))) …)
the first pattern would not apply at all, because this insn does notcontain two identical subexpressions in the right place. The pattern wouldsay, “That does not look like an add instruction; try other patterns”.The second pattern would say, “Yes, that’s an add instruction, but thereis something wrong with it”. It would direct the reload pass of thecompiler to generate additional insns to make the constraint true. Theresults might look like this:
(insnn2prevn (set (reg:SI 3) (reg:SI 6)) …)(insnnn2next (set (reg:SI 3) (plus:SI (reg:SI 3) (reg:SI 109))) …)
It is up to you to make sure that each operand, in each pattern, hasconstraints that can handle any RTL expression that could be present forthat operand. (When multiple alternatives are in use, each pattern must,for each possible combination of operand expressions, have at least onealternative which can handle that combination of operands.) Theconstraints don’t need toallow any possible operand—when this isthe case, they do not constrain—but they must at least point the way toreloading any possible operand so that it will fit.
For example, an operand whose constraints permit everything exceptregisters is safe provided its predicate rejects registers.
An operand whose predicate accepts only constant values is safeprovided its constraints include the letter ‘i’. If any possibleconstant value is accepted, then nothing less than ‘i’ will do;if the predicate is more selective, then the constraints may also bemore selective.
If the operand’s predicate can recognize registers, but the constraint doesnot permit them, it can make the compiler crash. When this operand happensto be a register, the reload pass will be stymied, because it does not knowhow to copy a register temporarily into memory.
If the predicate accepts a unary operator, the constraint applies to theoperand. For example, the MIPS processor at ISA level 3 supports aninstruction which adds two registers inSImode to produce aDImode result, but only if the registers are correctly signextended. This predicate for the input operands accepts asign_extend of anSImode register. Write the constraintto indicate the type of register that is required for the operand of thesign_extend.