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On many machines, the numbered registers are not all equivalent.For example, certain registers may not be allowed for indexed addressing;certain registers may not be allowed in some instructions. These machinerestrictions are described to the compiler usingregister classes.
You define a number of register classes, giving each one a name and sayingwhich of the registers belong to it. Then you can specify register classesthat are allowed as operands to particular instruction patterns.
In general, each register will belong to several classes. In fact, oneclass must be namedALL_REGS and contain all the registers. Anotherclass must be namedNO_REGS and contain no registers. Often theunion of two classes will be another class; however, this is not required.
One of the classes must be namedGENERAL_REGS. There is nothingterribly special about the name, but the operand constraint letters‘r’ and ‘g’ specify this class. IfGENERAL_REGS isthe same asALL_REGS, just define it as a macro which expandstoALL_REGS.
Order the classes so that if classx is contained in classythenx has a lower class number thany.
The way classes other thanGENERAL_REGS are specified in operandconstraints is through machine-dependent operand constraint letters.You can define such letters to correspond to various classes, then usethem in operand constraints.
You must define the narrowest register classes for allocatableregisters, so that each class either has no subclasses, or that forsome mode, the move cost between registers within the class ischeaper than moving a register in the class to or from memory(seeDescribing Relative Costs of Operations).
You should define a class for the union of two classes whenever someinstruction allows both classes. For example, if an instruction allowseither a floating point (coprocessor) register or a general register for acertain operand, you should define a classFLOAT_OR_GENERAL_REGSwhich includes both of them. Otherwise you will get suboptimal code,or even internal compiler errors when reload cannot find a register in theclass computed viareg_class_subunion.
You must also specify certain redundant information about the registerclasses: for each class, which classes contain it and which ones arecontained in it; for each pair of classes, the largest class containedin their union.
When a value occupying several consecutive registers is expected in acertain class, all the registers used must belong to that class.Therefore, register classes cannot be used to enforce a requirement fora register pair to start with an even-numbered register. The way tospecify this requirement is withTARGET_HARD_REGNO_MODE_OK,or with a filter expression in adefine_register_constraint.
Register classes used for input-operands of bitwise-and or shiftinstructions have a special requirement: each such class must have, foreach fixed-point machine mode, a subclass whose registers can transfer thatmode to or from memory. For example, on some machines, the operations forsingle-byte values (QImode) are limited to certain registers. Whenthis is so, each register class that is used in a bitwise-and or shiftinstruction must have a subclass consisting of registers from whichsingle-byte values can be loaded or stored. This is so thatPREFERRED_RELOAD_CLASS can always have a possible value to return.
An enumerated type that must be defined with all the register class namesas enumerated values.NO_REGS must be first.ALL_REGSmust be the last register class, followed by one more enumerated value,LIM_REG_CLASSES, which is not a register class but rathertells how many classes there are.
Each register class has a number, which is the value of castingthe class name to typeint. The number serves as an indexin many of the tables described below.
The number of distinct register classes, defined as follows:
#define N_REG_CLASSES (int) LIM_REG_CLASSES
An initializer containing the names of the register classes as C stringconstants. These names are used in writing some of the debugging dumps.
An initializer containing the contents of the register classes, as integerswhich are bit masks. Thenth integer specifies the contents of classn. The way the integermask is interpreted is thatregisterr is in the class ifmask & (1 <<r) is 1.
When the machine has more than 32 registers, an integer does not suffice.Then the integers are replaced by sub-initializers, braced groupings containingseveral integers. Each sub-initializer must be suitable as an initializerfor the typeHARD_REG_SET which is defined inhard-reg-set.h.In this situation, the first integer in each sub-initializer corresponds toregisters 0 through 31, the second integer to registers 32 through 63, andso on.
A C expression whose value is a register class containing hard registerregno. In general there is more than one such class; choose a classwhich isminimal, meaning that no smaller class also contains theregister.
A macro whose definition is the name of the class to which a validbase register must belong. A base register is one used in an addresswhich is the register value plus a displacement.
This is a variation of theBASE_REG_CLASS macro which allowsthe selection of a base register in a mode dependent manner. Ifmode is VOIDmode then it should return the same value asBASE_REG_CLASS.
A C expression whose value is the register class to which a validbase register must belong in order to be used in a base plus indexregister address. You should define this macro if base plus indexaddresses have different requirements than other base register uses.
A C expression whose value is the register class to which a validbase register for a memory reference in modemode to addressspaceaddress_space must belong.outer_code andindex_codedefine the context in which the base register occurs.outer_code isthe code of the immediately enclosing expression (MEM for the top levelof an address,ADDRESS for something that occurs in anaddress_operand).index_code is the code of the correspondingindex expression ifouter_code isPLUS;SCRATCH otherwise.
A C expression whose value is the register class to which a validbase register for a specifiedinsn must belong. This macro isused when some backend insns may have limited usage of base registercompared with other insns. If you define this macro, the compiler willuse it instead of all other defined macros that relate toBASE_REG_CLASS.
A macro whose definition is the name of the class to which a validindex register must belong. An index register is one used in anaddress where its value is either multiplied by a scale factor oradded to another register (as well as added to a displacement).
A C expression whose value is the register class to which a validindex register for a specifiedinsn must belong. This macro isused when some backend insns may have limited usage of index registercompared with other insns. If you defined this macro, the compilerwill use it instead ofINDEX_REG_CLASS.
A C expression which is nonzero if register numbernum issuitable for use as a base register in operand addresses.
A C expression that is just likeREGNO_OK_FOR_BASE_P, except thatthat expression may examine the mode of the memory reference inmode. You should define this macro if the mode of the memoryreference affects whether a register may be used as a base register. Ifyou define this macro, the compiler will use it instead ofREGNO_OK_FOR_BASE_P. The mode may beVOIDmode foraddresses that appear outside aMEM, i.e., as anaddress_operand.
A C expression which is nonzero if register numbernum is suitable foruse as a base register in base plus index operand addresses, accessingmemory in modemode. It may be either a suitable hard register or apseudo register that has been allocated such a hard register. You shoulddefine this macro if base plus index addresses have different requirementsthan other base register uses.
Use of this macro is deprecated; please use the more generalREGNO_MODE_CODE_OK_FOR_BASE_P.
A C expression which is nonzero if register numbernum issuitable for use as a base register in operand addresses, accessingmemory in modemode in address spaceaddress_space.This is similar toREGNO_MODE_OK_FOR_BASE_P, exceptthat that expression may examine the context in which the registerappears in the memory reference.outer_code is the code of theimmediately enclosing expression (MEM if at the top level of theaddress,ADDRESS for something that occurs in anaddress_operand).index_code is the code of thecorresponding index expression ifouter_code isPLUS;SCRATCH otherwise. The mode may beVOIDmode for addressesthat appear outside aMEM, i.e., as anaddress_operand.
A C expression which is nonzero if register numbernum issuitable for use as a base register in operand addresses for a specifiedinsn. This macro is used when some backend insn may have limitedusage of base register compared with other insns. If you define thismacro, the compiler will use it instead of all other defined macrosthat relate to REGNO_OK_FOR_BASE_P.
A C expression which is nonzero if register numbernum issuitable for use as an index register in operand addresses. It may beeither a suitable hard register or a pseudo register that has beenallocated such a hard register.
The difference between an index register and a base register is thatthe index register may be scaled. If an address involves the sum oftwo registers, neither one of them scaled, then either one may belabeled the “base” and the other the “index”; but whicheverlabeling is used must fit the machine’s constraints of which registersmay serve in each capacity. The compiler will try both labelings,looking for one that is valid, and will reload one or both registersonly if neither labeling works.
reg_class_tTARGET_PREFERRED_RENAME_CLASS(reg_class_trclass) ¶A target hook that places additional preference on the registerclass to use when it is necessary to rename a register in classrclass to another class, or perhapsNO_REGS, if nopreferred register class is found or hookpreferred_rename_classis not implemented.Sometimes returning a more restrictive class makes better code. Forexample, on ARM, thumb-2 instructions usingLO_REGS may besmaller than instructions usingGENERIC_REGS. By returningLO_REGS frompreferred_rename_class, code size canbe reduced.
reg_class_tTARGET_PREFERRED_RELOAD_CLASS(rtxx, reg_class_trclass) ¶A target hook that places additional restrictions on the register classto use when it is necessary to copy valuex into a register in classrclass. The value is a register class; perhapsrclass, or perhapsanother, smaller class.
The default version of this hook always returns value ofrclass argument.
Sometimes returning a more restrictive class makes better code. Forexample, on the 68000, whenx is an integer constant that is in rangefor a ‘moveq’ instruction, the value of this macro is alwaysDATA_REGS as long asrclass includes the data registers.Requiring a data register guarantees that a ‘moveq’ will be used.
One case whereTARGET_PREFERRED_RELOAD_CLASS must not returnrclass is ifx is a legitimate constant which cannot beloaded into some register class. By returningNO_REGS you canforcex into a memory location. For example, rs6000 can loadimmediate values into general-purpose registers, but does not have aninstruction for loading an immediate value into a floating-pointregister, soTARGET_PREFERRED_RELOAD_CLASS returnsNO_REGS whenx is a floating-point constant. If the constant can’t be loadedinto any kind of register, code generation will be better ifTARGET_LEGITIMATE_CONSTANT_P makes the constant illegitimate insteadof usingTARGET_PREFERRED_RELOAD_CLASS.
If an insn has pseudos in it after register allocation, reload will gothrough the alternatives and call repeatedlyTARGET_PREFERRED_RELOAD_CLASSto find the best one. ReturningNO_REGS, in this case, makesreload add a! in front of the constraint: the x86 back-end usesthis feature to discourage usage of 387 registers when math is done inthe SSE registers (and vice versa).
A C expression that places additional restrictions on the register classto use when it is necessary to copy valuex into a register in classclass. The value is a register class; perhapsclass, or perhapsanother, smaller class. On many machines, the following definition issafe:
#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
Sometimes returning a more restrictive class makes better code. Forexample, on the 68000, whenx is an integer constant that is in rangefor a ‘moveq’ instruction, the value of this macro is alwaysDATA_REGS as long asclass includes the data registers.Requiring a data register guarantees that a ‘moveq’ will be used.
One case wherePREFERRED_RELOAD_CLASS must not returnclass is ifx is a legitimate constant which cannot beloaded into some register class. By returningNO_REGS you canforcex into a memory location. For example, rs6000 can loadimmediate values into general-purpose registers, but does not have aninstruction for loading an immediate value into a floating-pointregister, soPREFERRED_RELOAD_CLASS returnsNO_REGS whenx is a floating-point constant. If the constant cannot be loadedinto any kind of register, code generation will be better ifTARGET_LEGITIMATE_CONSTANT_P makes the constant illegitimate insteadof usingTARGET_PREFERRED_RELOAD_CLASS.
If an insn has pseudos in it after register allocation, reload will gothrough the alternatives and call repeatedlyPREFERRED_RELOAD_CLASSto find the best one. ReturningNO_REGS, in this case, makesreload add a! in front of the constraint: the x86 back-end usesthis feature to discourage usage of 387 registers when math is done inthe SSE registers (and vice versa).
reg_class_tTARGET_PREFERRED_OUTPUT_RELOAD_CLASS(rtxx, reg_class_trclass) ¶LikeTARGET_PREFERRED_RELOAD_CLASS, but for output reloads instead ofinput reloads.
The default version of this hook always returns value ofrclassargument.
You can also useTARGET_PREFERRED_OUTPUT_RELOAD_CLASS to discouragereload from using some alternatives, likeTARGET_PREFERRED_RELOAD_CLASS.
A C expression that places additional restrictions on the register classto use when it is necessary to be able to hold a value of modemode in a reload register for which classclass wouldordinarily be used.
UnlikePREFERRED_RELOAD_CLASS, this macro should be used whenthere are certain modes that simply cannot go in certain reload classes.
The value is a register class; perhapsclass, or perhaps another,smaller class.
Don’t define this macro unless the target machine has limitations whichrequire the macro to do something nontrivial.
reg_class_tTARGET_SECONDARY_RELOAD(boolin_p, rtxx, reg_class_treload_class, machine_modereload_mode, secondary_reload_info *sri) ¶Many machines have some registers that cannot be copied directly to orfrom memory or even from other types of registers. An example is the‘MQ’ register, which on most machines, can only be copied to orfrom general registers, but not memory. Below, we shall be using theterm ’intermediate register’ when a move operation cannot be performeddirectly, but has to be done by copying the source into the intermediateregister first, and then copying the intermediate register to thedestination. An intermediate register always has the same mode assource and destination. Since it holds the actual value being copied,reload might apply optimizations to re-use an intermediate registerand eliding the copy from the source when it can determine that theintermediate register still holds the required value.
Another kind of secondary reload is required on some machines whichallow copying all registers to and from memory, but require a scratchregister for stores to some memory locations (e.g., those with symbolicaddress on the RT, and those with certain symbolic address on the SPARCwhen compiling PIC). Scratch registers need not have the same modeas the value being copied, and usually hold a different value thanthat being copied. Special patterns in the md file are needed todescribe how the copy is performed with the help of the scratch register;these patterns also describe the number, register class(es) and mode(s)of the scratch register(s).
In some cases, both an intermediate and a scratch register are required.
For input reloads, this target hook is called with nonzeroin_p,andx is an rtx that needs to be copied to a register of classreload_class inreload_mode. For output reloads, this targethook is called with zeroin_p, and a register of classreload_classneeds to be copied to rtxx inreload_mode.
If copying a register ofreload_class from/tox requiresan intermediate register, the hooksecondary_reload shouldreturn the register class required for this intermediate register.If no intermediate register is required, it should return NO_REGS.If more than one intermediate register is required, describe the onethat is closest in the copy chain to the reload register.
If scratch registers are needed, you also have to describe how toperform the copy from/to the reload register to/from thisclosest intermediate register. Or if no intermediate register isrequired, but still a scratch register is needed, describe thecopy from/to the reload register to/from the reload operandx.
You do this by settingsri->icode to the instruction code of a patternin the md file which performs the move. Operands 0 and 1 are the outputand input of this copy, respectively. Operands from operand 2 onward arefor scratch operands. These scratch operands must have a mode, and asingle-register-classoutput constraint.
When an intermediate register is used, thesecondary_reloadhook will be called again to determine how to copy the intermediateregister to/from the reload operandx, so your hook must alsohave code to handle the register class of the intermediate operand.
x might be a pseudo-register or asubreg of apseudo-register, which could either be in a hard register or in memory.Usetrue_regnum to find out; it will return −1 if the pseudo isin memory and the hard register number if it is in a register.
Scratch operands in memory (constraint"=m" /"=&m") arecurrently not supported. For the time being, you will have to continueto useTARGET_SECONDARY_MEMORY_NEEDED for that purpose.
copy_cost also uses this target hook to find out how values arecopied. If you want it to include some extra cost for the need to allocate(a) scratch register(s), setsri->extra_cost to the additional cost.Or if two dependent moves are supposed to have a lower cost than the sumof the individual moves due to expected fortuitous scheduling and/or specialforwarding logic, you can setsri->extra_cost to a negative amount.
These macros are obsolete, new ports should use the target hookTARGET_SECONDARY_RELOAD instead.
These are obsolete macros, replaced by theTARGET_SECONDARY_RELOADtarget hook. Older ports still define these macros to indicate to thereload phase that it mayneed to allocate at least one register for a reload in addition to theregister to contain the data. Specifically, if copyingx to aregisterclass inmode requires an intermediate register,you were supposed to defineSECONDARY_INPUT_RELOAD_CLASS to return thelargest register class all of whose registers can be used asintermediate registers or scratch registers.
If copying a registerclass inmode tox requires anintermediate or scratch register,SECONDARY_OUTPUT_RELOAD_CLASSwas supposed to be defined to return the largest registerclass required. If therequirements for input and output reloads were the same, the macroSECONDARY_RELOAD_CLASS should have been used instead of defining bothmacros identically.
The values returned by these macros are oftenGENERAL_REGS.ReturnNO_REGS if no spare register is needed; i.e., ifxcan be directly copied to or from a register ofclass inmode without requiring a scratch register. Do not define thismacro if it would always returnNO_REGS.
If a scratch register is required (either with or without anintermediate register), you were supposed to define patterns for‘reload_inm’ or ‘reload_outm’, as required(seeStandard Pattern Names For Generation. These patterns, which were normallyimplemented with adefine_expand, should be similar to the‘movm’ patterns, except that operand 2 is the scratchregister.
These patterns need constraints for the reload register and scratchregister thatcontain a single register class. If the original reload register (whoseclass isclass) can meet the constraint given in the pattern, thevalue returned by these macros is used for the class of the scratchregister. Otherwise, two additional reload registers are required.Their classes are obtained from the constraints in the insn pattern.
x might be a pseudo-register or asubreg of apseudo-register, which could either be in a hard register or in memory.Usetrue_regnum to find out; it will return −1 if the pseudo isin memory and the hard register number if it is in a register.
These macros should not be used in the case where a particular class ofregisters can only be copied to memory and not to another class ofregisters. In that case, secondary reload registers are not needed andwould not be helpful. Instead, a stack location must be used to performthe copy and themovm pattern should use memory as anintermediate storage. This case often occurs between floating-point andgeneral registers.
boolTARGET_SECONDARY_MEMORY_NEEDED(machine_modemode, reg_class_tclass1, reg_class_tclass2) ¶Certain machines have the property that some registers cannot be copiedto some other registers without using memory. Define this hook onthose machines to return true if objects of modem in registersofclass1 can only be copied to registers of classclass2 by storing a register ofclass1 into memory and loading that memorylocation into a register ofclass2. The default definition returnsfalse for all inputs.
Normally whenTARGET_SECONDARY_MEMORY_NEEDED is defined, the compilerallocates a stack slot for a memory location needed for register copies.If this macro is defined, the compiler instead uses the memory locationdefined by this macro.
Do not define this macro if you do not defineTARGET_SECONDARY_MEMORY_NEEDED.
machine_modeTARGET_SECONDARY_MEMORY_NEEDED_MODE(machine_modemode) ¶IfTARGET_SECONDARY_MEMORY_NEEDED tells the compiler to use memorywhen moving between two particular registers of modemode,this hook specifies the mode that the memory should have.
The default depends onTARGET_LRA_P. Without LRA, the defaultis to use a word-sized mode for integral modes that are smaller than aa word. This is right thing to do on most machines because it ensuresthat all bits of the register are copied and prevents accesses to theregisters in a narrower mode, which some machines prohibit forfloating-point registers.
However, this default behavior is not correct on some machines, such asthe DEC Alpha, that store short integers in floating-point registersdifferently than in integer registers. On those machines, the defaultwidening will not work correctly and you must define this hook tosuppress that widening in some cases. See the filealpha.cc fordetails.
With LRA, the default is to usemode unmodified.
voidTARGET_SELECT_EARLY_REMAT_MODES(sbitmapmodes) ¶On some targets, certain modes cannot be held in registers around astandard ABI call and are relatively expensive to spill to the stack.The early rematerialization pass can help in such cases by aggressivelyrecomputing values after calls, so that they don’t need to be spilled.
This hook returns the set of such modes by setting the associated bitsinmodes. The default implementation selects no modes, which hasthe effect of disabling the early rematerialization pass.
boolTARGET_CLASS_LIKELY_SPILLED_P(reg_class_trclass) ¶A target hook which returnstrue if pseudos that have been assignedto registers of classrclass would likely be spilled becauseregisters ofrclass are needed for spill registers.
The default version of this target hook returnstrue ifrclasshas exactly one register andfalse otherwise. On most machines, thisdefault should be used. For generally register-starved machines, such asi386, or machines with right register constraints, such as SH, this hookcan be used to avoid excessive spilling.
This hook is also used by some of the global intra-procedural codetransformations to throtle code motion, to avoid increasing registerpressure.
unsigned charTARGET_CLASS_MAX_NREGS(reg_class_trclass, machine_modemode) ¶A target hook returns the maximum number of consecutive registersof classrclass needed to hold a value of modemode.
This is closely related to the macroTARGET_HARD_REGNO_NREGS.In fact, the value returned byTARGET_CLASS_MAX_NREGS (rclass,mode) target hook should be the maximum value ofTARGET_HARD_REGNO_NREGS (regno,mode) for allregnovalues in the classrclass.
This target hook helps control the handling of multiple-word valuesin the reload pass.
The default version of this target hook returns the size ofmodein words.
A C expression for the maximum number of consecutive registersof classclass needed to hold a value of modemode.
This is closely related to the macroTARGET_HARD_REGNO_NREGS. In fact,the value of the macroCLASS_MAX_NREGS (class,mode)should be the maximum value ofTARGET_HARD_REGNO_NREGS (regno,mode) for allregno values in the classclass.
This macro helps control the handling of multiple-word valuesin the reload pass.
boolTARGET_CAN_CHANGE_MODE_CLASS(machine_modefrom, machine_modeto, reg_class_trclass) ¶This hook returns true if it is possible to bitcast values held inregisters of classrclass from modefrom to modetoand if doing so preserves the low-order bits that are common to both modes.The result is only meaningful ifrclass has registers that can holdbothfrom andto. The default implementation returns true.
As an example of when such bitcasting is invalid, loading 32-bit integer orfloating-point objects into floating-point registers on Alpha extends themto 64 bits. Therefore loading a 64-bit object and then storing it as a32-bit object does not store the low-order 32 bits, as would be the casefor a normal register. Therefore,alpha.h definesTARGET_CAN_CHANGE_MODE_CLASS to return:
(GET_MODE_SIZE (from) == GET_MODE_SIZE (to) || !reg_classes_intersect_p (FLOAT_REGS, rclass))
Even if storing from a register in modeto would be valid,if bothfrom andraw_reg_mode forrclass are widerthanword_mode, then we must preventto narrowing themode. This happens when the middle-end assumes that it can loador store pieces of anN-word pseudo, and that the pseudo willeventually be allocated toNword_mode hard registers.Failure to prevent this kind of mode change will result in theentireraw_reg_mode being modified instead of the partialvalue that the middle-end intended.
reg_class_tTARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS(int,reg_class_t,reg_class_t) ¶A target hook which can change allocno class for given pseudo from allocno and best class calculated by IRA.
The default version of this target hook always returns given class.
boolTARGET_LRA_P(void) ¶A target hook which returns true if we use LRA instead of reload pass.
The default version of this target hook returns true. New portsshould use LRA, and existing ports are encouraged to convert.
intTARGET_REGISTER_PRIORITY(int) ¶A target hook which returns the register priority number to which theregisterhard_regno belongs to. The bigger the number, themore preferable the hard register usage (when all other conditions arethe same). This hook can be used to prefer some hard register overothers in LRA. For example, some x86-64 register usage needsadditional prefix which makes instructions longer. The hook canreturn lower priority number for such registers make them less favorableand as result making the generated code smaller.
The default version of this target hook returns always zero.
boolTARGET_REGISTER_USAGE_LEVELING_P(void) ¶A target hook which returns true if we need register usage leveling.That means if a few hard registers are equally good for theassignment, we choose the least used hard register. The registerusage leveling may be profitable for some targets. Don’t use theusage leveling for targets with conditional execution or targetswith big register files as it hurts if-conversion and cross-jumpingoptimizations.
The default version of this target hook returns always false.
boolTARGET_DIFFERENT_ADDR_DISPLACEMENT_P(void) ¶A target hook which returns true if an address with the same structurecan have different maximal legitimate displacement. For example, thedisplacement can depend on memory mode or on operand combinations inthe insn.
The default version of this target hook returns always false.
boolTARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P(rtxsubst) ¶A target hook which returnstrue ifsubst can’tsubstitute safely pseudos with equivalent memory values duringregister allocation.The default version of this target hook returnsfalse.On most machines, this default should be used. For generallymachines with non orthogonal register usage for addressing, suchas SH, this hook can be used to avoid excessive spilling.
boolTARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT(rtx *offset1, rtx *offset2, poly_int64orig_offset, machine_modemode) ¶This hook tries to split address offsetorig_offset intotwo parts: one that should be added to the base address to createa local anchor point, and an additional offset that can be appliedto the anchor to address a value of modemode. The idea is thatthe local anchor could be shared by other accesses to nearby locations.
The hook returns true if it succeeds, storing the offset of theanchor from the base inoffset1 and the offset of the final addressfrom the anchor inoffset2. The default implementation returns false.
reg_class_tTARGET_SPILL_CLASS(reg_class_t,machine_mode) ¶This hook defines a class of registers which could be used for spillingpseudos of the given mode and class, orNO_REGS if only memoryshould be used. Not defining this hook is equivalent to returningNO_REGS for all inputs.
boolTARGET_ADDITIONAL_ALLOCNO_CLASS_P(reg_class_t) ¶This hook should returntrue if given class of registers shouldbe an allocno class in any way. Usually RA uses only one registerclass from all classes containing the same register set. In somecomplicated cases, you need to have two or more such classes asallocno ones for RA correct work. Not defining this hook isequivalent to returningfalse for all inputs.
scalar_int_modeTARGET_CSTORE_MODE(enum insn_codeicode) ¶This hook defines the machine mode to use for the boolean result ofconditional store patterns. The ICODE argument is the instruction codefor the cstore being performed. Not definiting this hook is the sameas accepting the mode encoded into operand 0 of the cstore expanderpatterns.
intTARGET_COMPUTE_PRESSURE_CLASSES(enum reg_class *pressure_classes) ¶A target hook which lets a backend compute the set of pressure classes tobe used by those optimization passes which take register pressure intoaccount, as opposed to letting IRA compute them. It returns the number ofregister classes stored in the arraypressure_classes.
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