Next:Example ofdefine_insn, Previous:Overview of How the Machine Description is Used, Up:Machine Descriptions [Contents][Index]
Adefine_insn expression is used to define instruction patternsto which insns may be matched. Adefine_insn expression containsan incomplete RTL expression, with pieces to be filled in later, operandconstraints that restrict how the pieces can be filled in, and an outputtemplate or C code to generate the assembler output.
Adefine_insn is an RTL expression containing four or five operands:
insn_code.These names serve one of two purposes. The first is to indicate that theinstruction performs a certain standard job for the RTL-generationpass of the compiler, such as a move, an addition, or a conditionaljump. The second is to help the target generate certain target-specificoperations, such as when implementing target-specific intrinsic functions.
It is better to prefix target-specific names with the name of thetarget, to avoid any clash with current or future standard names.
The absence of a name is indicated by writing an empty stringwhere the name should go. Nameless instruction patterns are neverused for generating RTL code, but they may permit several simpler insnsto be combined later on.
For the purpose of debugging the compiler, you may also specify aname beginning with the ‘*’ character. Such a name is used onlyfor identifying the instruction in RTL dumps; it is equivalent to havinga nameless pattern for all other purposes. Names beginning with the‘*’ character are not required to be unique.
The name may also have the form ‘@n’. This has the sameeffect as a name ‘n’, but in addition tells the compiler togenerate further helper functions; seeParameterized Names for details.
match_operand,match_operator, andmatch_dup expressions that stand foroperands of the instruction.If the vector has multiple elements, the RTL template is treated as aparallel expression.
true, the match ispermitted. The condition may be an empty string, which is treatedas alwaystrue.For a named pattern, the condition may not depend on the data in theinsn being matched, but only the target-machine-type flags. The compilerneeds to test these conditions during initialization in order to learnexactly which named instructions are available in a particular run.
For nameless patterns, the condition is applied only when matching anindividual insn, and only after the insn has matched the pattern’srecognition template. The insn’s operands may be found in the vectoroperands.
An instruction condition cannot become more restrictive as compilationprogresses. If the condition accepts a particular RTL instruction atone stage of compilation, it must continue to accept that instructionuntil the final pass. For example, ‘!reload_completed’ and‘can_create_pseudo_p ()’ are both invalid instruction conditions,because they are true during the earlier RTL passes and false duringthe later ones. For the same reason, if a condition accepts aninstruction before register allocation, it cannot later try to controlregister allocation by excluding certain register or value combinations.
Although a condition cannot become more restrictive as compilationprogresses, the condition for a nameless patterncan becomemore permissive. For example, a nameless instruction can require‘reload_completed’ to be true, in which case it only matchesafter register allocation.
When simple substitution isn’t general enough, you can specify a pieceof C code to compute the output. SeeC Statements for Assembler Output.
Next:Example ofdefine_insn, Previous:Overview of How the Machine Description is Used, Up:Machine Descriptions [Contents][Index]