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16.9.5 Constraints for Particular Machines ¶

Whenever possible, you should use the general-purpose constraint lettersinasm arguments, since they will convey meaning more readily topeople reading your code. Failing that, use the constraint lettersthat usually have very similar meanings across architectures. The mostcommonly used constraints are ‘m’ and ‘r’ (for memory andgeneral-purpose registers respectively; seeSimple Constraints), and‘I’, usually the letter indicating the most commonimmediate-constant format.

Each architecture defines additional constraints. These constraintsare used by the compiler itself for instruction generation, as well asforasm statements; therefore, some of the constraints are notparticularly useful forasm. Here is a summary of some of themachine-dependent constraints available on some particular machines;it includes both constraints that are useful forasm andconstraints that aren’t. The compiler source file mentioned in thetable heading for each architecture is the definitive reference forthe meanings of that architecture’s constraints.

AArch64 family—config/aarch64/constraints.md

k: The stack pointer register (SP)
w: Floating point register, Advanced SIMD vector register or SVE vector register
x: Likew, but restricted to registers 0 to 15 inclusive.
y: Likew, but restricted to registers 0 to 7 inclusive.
Upl: One of the low eight SVE predicate registers (P0 toP7)
Upa: Any of the SVE predicate registers (P0 toP15)
I: Integer constant that is valid as an immediate operand in anADDinstruction
J: Integer constant that is valid as an immediate operand in aSUBinstruction (once negated)
K: Integer constant that can be used with a 32-bit logical instruction
L: Integer constant that can be used with a 64-bit logical instruction
M: Integer constant that is valid as an immediate operand in a 32-bitMOVpseudo instruction. TheMOV may be assembled to one of several differentmachine instructions depending on the value
N: Integer constant that is valid as an immediate operand in a 64-bitMOVpseudo instruction
S: An absolute symbolic address or a label reference
Y: Floating point constant zero
Z: Integer constant zero
Ush: The high part (bits 12 and upwards) of the pc-relative address of a symbolwithin 4GB of the instruction
Q: A memory address which uses a single base register with no offset
Ump: A memory address suitable for a load/store pair instruction in SI, DI, SF andDF modes

AMD GCN —config/gcn/constraints.md

I: Immediate integer in the range −16 to 64
J: Immediate 16-bit signed integer
Kf: Immediate constant −1
L: Immediate 15-bit unsigned integer
A: Immediate constant that can be inlined in an instruction encoding: integer−16..64, or float 0.0, +/−0.5, +/−1.0, +/−2.0,+/−4.0, 1.0/(2.0*PI)
B: Immediate 32-bit signed integer that can be attached to an instruction encoding
C: Immediate 32-bit integer in range −16..4294967295 (i.e. 32-bit unsignedinteger or ‘A’ constraint)
DA: Immediate 64-bit constant that can be split into two ‘A’ constants
DB: Immediate 64-bit constant that can be split into two ‘B’ constants
U: Anyunspec
Y: Anysymbol_ref orlabel_ref
v: VGPR register
a: Accelerator VGPR register (CDNA1 onwards)
Sg: SGPR register
SD: SGPR registers valid for instruction destinations, including VCC, M0 and EXEC
SS: SGPR registers valid for instruction sources, including VCC, M0, EXEC and SCC
Sm: SGPR registers valid as a source for scalar memory instructions (excludes M0and EXEC)
Sv: SGPR registers valid as a source or destination for vector instructions(excludes EXEC)
ca: All condition registers: SCC, VCCZ, EXECZ
cs: Scalar condition register: SCC
cV: Vector condition register: VCC, VCC_LO, VCC_HI
e: EXEC register (EXEC_LO and EXEC_HI)
RB: Memory operand with address space suitable forbuffer_* instructions
RF: Memory operand with address space suitable forflat_* instructions
RS: Memory operand with address space suitable fors_* instructions
RL: Memory operand with address space suitable fords_* LDS instructions
RG: Memory operand with address space suitable fords_* GDS instructions
RD: Memory operand with address space suitable for anyds_* instructions
RM: Memory operand with address space suitable forglobal_* instructions

ARC —config/arc/constraints.md

q: Registers usable in ARCompact 16-bit instructions:r0-r3,r12-r15. This constraint can only match when the-mqoption is in effect.
e: Registers usable as base-regs of memory addresses in ARCompact 16-bit memoryinstructions:r0-r3,r12-r15,sp.This constraint can only match when the-mqoption is in effect.
D: ARC FPX (dpfp) 64-bit registers.D0,D1.
I: A signed 12-bit integer constant.
Cal: constant for arithmetic/logical operations. This might be any constantthat can be put into a long immediate by the assmbler or linker withoutinvolving a PIC relocation.
K: A 3-bit unsigned integer constant.
L: A 6-bit unsigned integer constant.
CnL: One’s complement of a 6-bit unsigned integer constant.
CmL: Two’s complement of a 6-bit unsigned integer constant.
M: A 5-bit unsigned integer constant.
O: A 7-bit unsigned integer constant.
P: A 8-bit unsigned integer constant.
H: Any const_double value.

ARM family—config/arm/constraints.md

h: In Thumb state, the core registersr8-r15.
k: The stack pointer register.
l: In Thumb State the core registersr0-r7. In ARM state thisis an alias for ther constraint.
t: VFP floating-point registerss0-s31. Used for 32 bit values.
w: VFP floating-point registersd0-d31 and the appropriatesubsetd0-d15 based on command line options.Used for 64 bit values only. Not valid for Thumb1.
G: The floating-point constant 0.0
I: Integer that is valid as an immediate operand in a data processinginstruction. That is, an integer in the range 0 to 255 rotated by amultiple of 2
J: Integer in the range −4095 to 4095
K: Integer that satisfies constraint ‘I’ when inverted (ones complement)
L: Integer that satisfies constraint ‘I’ when negated (twos complement)
M: Integer in the range 0 to 32
Q: A memory reference where the exact address is in a single register(‘‘m’’ is preferable forasm statements)
R: An item in the constant pool
S: A symbol in the text segment of the current file
Uv: A memory reference suitable for VFP load/store insns (reg+constant offset)
Uq: A memory reference suitable for the ARMv4 ldrsb instruction.

AVR family—config/avr/constraints.md

l: Registers from r0 to r15
a: Registers from r16 to r23
d: Registers from r16 to r31
w: Registers from r24 to r31. These registers can be used in ‘adiw’ command
e: Pointer register (r26–r31)
b: Base pointer register (r28–r31)
q: Stack pointer register (SPH:SPL)
t: Temporary register r0
x: Register pair X (r27:r26)
y: Register pair Y (r29:r28)
z: Register pair Z (r31:r30)
I: Constant greater than −1, less than 64
J: Constant greater than −64, less than 1
K: Constant integer 2
L: Constant integer 0
M: Constant that fits in 8 bits
N: Constant integer −1
O: Constant integer 8, 16, or 24
P: Constant integer 1
G: A floating point constant 0.0
Q: A memory address based on Y or Z pointer with displacement.

Blackfin family—config/bfin/constraints.md

a: P register
d: D register
z: A call clobbered P register.
qn: A single register. Ifn is in the range 0 to 7, the corresponding Dregister. If it isA, then the register P0.
D: Even-numbered D register
W: Odd-numbered D register
e: Accumulator register.
A: Even-numbered accumulator register.
B: Odd-numbered accumulator register.
b: I register
v: B register
f: M register
c: Registers used for circular buffering, i.e. I, B, or L registers.
C: The CC register.
t: LT0 or LT1.
k: LC0 or LC1.
u: LB0 or LB1.
x: Any D, P, B, M, I or L register.
y: Additional registers typically used only in prologues and epilogues: RETS,RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
w: Any register except accumulators or CC.
Ksh: Signed 16 bit integer (in the range −32768 to 32767)
Kuh: Unsigned 16 bit integer (in the range 0 to 65535)
Ks7: Signed 7 bit integer (in the range −64 to 63)
Ku7: Unsigned 7 bit integer (in the range 0 to 127)
Ku5: Unsigned 5 bit integer (in the range 0 to 31)
Ks4: Signed 4 bit integer (in the range −8 to 7)
Ks3: Signed 3 bit integer (in the range −3 to 4)
Ku3: Unsigned 3 bit integer (in the range 0 to 7)
Pn: Constantn, wheren is a single-digit constant in the range 0 to 4.
PA: An integer equal to one of the MACFLAG_XXX constants that is suitable foruse with either accumulator.
PB: An integer equal to one of the MACFLAG_XXX constants that is suitable foruse only with accumulator A1.
M1: Constant 255.
M2: Constant 65535.
J: An integer constant with exactly a single bit set.
L: An integer constant with all bits set except exactly one.
H
Q: Any SYMBOL_REF.

C-SKY—config/csky/constraints.md

a: The mini registers r0 - r7.
b: The low registers r0 - r15.
c: C register.
y: HI and LO registers.
l: LO register.
h: HI register.
v: Vector registers.
z: Stack pointer register (SP).
Q: A memory address which uses a base register with a short offsetor with a index register with its scale.
W: A memory address which uses a base register with a index registerwith its scale.

The C-SKY back end supports a large set of additional constraintsthat are only useful for instruction selection or splitting ratherthan inline asm, such as constraints representing constant integerranges accepted by particular instruction encodings.Refer to the source code for details.

Epiphany—config/epiphany/constraints.md

U16: An unsigned 16-bit constant.
K: An unsigned 5-bit constant.
L: A signed 11-bit constant.
Cm1: A signed 11-bit constant added to −1.Can only match when the-m1reg-reg option is active.
Cl1: Left-shift of −1, i.e., a bit mask with a block of leading ones, the restbeing a block of trailing zeroes.Can only match when the-m1reg-reg option is active.
Cr1: Right-shift of −1, i.e., a bit mask with a trailing block of ones, therest being zeroes. Or to put it another way, one less than a power of two.Can only match when the-m1reg-reg option is active.
Cal: Constant for arithmetic/logical operations.This is likei, except that for position independent code,no symbols / expressions needing relocations are allowed.
Csy: Symbolic constant for call/jump instruction.
Rcs: The register class usable in short insns. This is a register classconstraint, and can thus drive register allocation.This constraint won’t match unless-mprefer-short-insn-regs isin effect.
Rsc: The register class of registers that can be used to hold asibcall call address. I.e., a caller-saved register.
Rct: Core control register class.
Rgs: The register group usable in short insns.This constraint does not use a register class, so that it onlypassively matches suitable registers, and doesn’t drive register allocation.
Car: Constant suitable for the addsi3_r pattern. This is a valid offsetFor byte, halfword, or word addressing.
Rra: Matches the return address if it can be replaced with the link register.
Rcc: Matches the integer condition code register.
Sra: Matches the return address if it is in a stack slot.
Cfm: Matches control register values to switch fp mode, which are encapsulated inUNSPEC_FP_MODE.

FRV—config/frv/frv.h

a: Register in the classACC_REGS (acc0 toacc7).
b: Register in the classEVEN_ACC_REGS (acc0 toacc7).
c: Register in the classCC_REGS (fcc0 tofcc3 andicc0 toicc3).
d: Register in the classGPR_REGS (gr0 togr63).
e: Register in the classEVEN_REGS (gr0 togr63).Odd registers are excluded not in the class but through the use of a machinemode larger than 4 bytes.
f: Register in the classFPR_REGS (fr0 tofr63).
h: Register in the classFEVEN_REGS (fr0 tofr63).Odd registers are excluded not in the class but through the use of a machinemode larger than 4 bytes.
l: Register in the classLR_REG (thelr register).
q: Register in the classQUAD_REGS (gr2 togr63).Register numbers not divisible by 4 are excluded not in the class but throughthe use of a machine mode larger than 8 bytes.
t: Register in the classICC_REGS (icc0 toicc3).
u: Register in the classFCC_REGS (fcc0 tofcc3).
v: Register in the classICR_REGS (cc4 tocc7).
w: Register in the classFCR_REGS (cc0 tocc3).
x: Register in the classQUAD_FPR_REGS (fr0 tofr63).Register numbers not divisible by 4 are excluded not in the class but throughthe use of a machine mode larger than 8 bytes.
z: Register in the classSPR_REGS (lcr andlr).
A: Register in the classQUAD_ACC_REGS (acc0 toacc7).
B: Register in the classACCG_REGS (accg0 toaccg7).
C: Register in the classCR_REGS (cc0 tocc7).
G: Floating point constant zero
I: 6-bit signed integer constant
J: 10-bit signed integer constant
L: 16-bit signed integer constant
M: 16-bit unsigned integer constant
N: 12-bit signed integer constant that is negative—i.e. in therange of −2048 to −1
O: Constant zero
P: 12-bit signed integer constant that is greater than zero—i.e. in therange of 1 to 2047.

FT32—config/ft32/constraints.md

A: An absolute address
B: An offset address
W: A register indirect memory operand
e: An offset address.
f: An offset address.
O: The constant zero or one
I: A 16-bit signed constant (−32768 … 32767)
w: A bitfield mask suitable for bext or bins
x: An inverted bitfield mask suitable for bext or bins
L: A 16-bit unsigned constant, multiple of 4 (0 … 65532)
S: A 20-bit signed constant (−524288 … 524287)
b: A constant for a bitfield width (1 … 16)
KA: A 10-bit signed constant (−512 … 511)

Hewlett-Packard PA-RISC—config/pa/pa.h

a: General register 1
f: Floating point register
q: Shift amount register
x: Floating point register (deprecated)
y: Upper floating point register (32-bit), floating point register (64-bit)
Z: Any register
I: Signed 11-bit integer constant
J: Signed 14-bit integer constant
K: Integer constant that can be deposited with azdepi instruction
L: Signed 5-bit integer constant
M: Integer constant 0
N: Integer constant that can be loaded with aldil instruction
O: Integer constant whose value plus one is a power of 2
P: Integer constant that can be used forand operations indepiandextru instructions
S: Integer constant 31
U: Integer constant 63
G: Floating-point constant 0.0
A: Alo_sum data-linkage-table memory operand
Q: A memory operand that can be used as the destination operand of aninteger store instruction
R: A scaled or unscaled indexed memory operand
T: A memory operand for floating-point loads and stores
W: A register indirect memory operand

Intel IA-64—config/ia64/ia64.h

a: General registerr0 tor3 foraddl instruction
b: Branch register
c: Predicate register (‘c’ as in “conditional”)
d: Application register residing in M-unit
e: Application register residing in I-unit
f: Floating-point register
m: Memory operand. If used together with ‘<’ or ‘>’,the operand can have postincrement and postdecrement whichrequire printing with ‘%Pn’ on IA-64.
G: Floating-point constant 0.0 or 1.0
I: 14-bit signed integer constant
J: 22-bit signed integer constant
K: 8-bit signed integer constant for logical instructions
L: 8-bit adjusted signed integer constant for compare pseudo-ops
M: 6-bit unsigned integer constant for shift counts
N: 9-bit signed integer constant for load and store postincrements
O: The constant zero
P: 0 or −1 fordep instruction
Q: Non-volatile memory for floating-point loads and stores
R: Integer constant in the range 1 to 4 forshladd instruction
S: Memory operand except postincrement and postdecrement. This isnow roughly the same as ‘m’ when not used together with ‘<’or ‘>’.

M32C—config/m32c/m32c.cc

Rsp
Rfb
Rsb: ‘$sp’, ‘$fb’, ‘$sb’.
Rcr: Any control register, when they’re 16 bits wide (nothing if controlregisters are 24 bits wide)
Rcl: Any control register, when they’re 24 bits wide.
R0w
R1w
R2w
R3w: $r0, $r1, $r2, $r3.
R02: $r0 or $r2, or $r2r0 for 32 bit values.
R13: $r1 or $r3, or $r3r1 for 32 bit values.
Rdi: A register that can hold a 64 bit value.
Rhl: $r0 or $r1 (registers with addressable high/low bytes)
R23: $r2 or $r3
Raa: Address registers
Raw: Address registers when they’re 16 bits wide.
Ral: Address registers when they’re 24 bits wide.
Rqi: Registers that can hold QI values.
Rad: Registers that can be used with displacements ($a0, $a1, $sb).
Rsi: Registers that can hold 32 bit values.
Rhi: Registers that can hold 16 bit values.
Rhc: Registers chat can hold 16 bit values, including all controlregisters.
Rra: $r0 through R1, plus $a0 and $a1.
Rfl: The flags register.
Rmm: The memory-based pseudo-registers $mem0 through $mem15.
Rpi: Registers that can hold pointers (16 bit registers for r8c, m16c; 24bit registers for m32cm, m32c).
Rpa: Matches multiple registers in a PARALLEL to form a larger register.Used to match function return values.
Is3: −8 … 7
IS1: −128 … 127
IS2: −32768 … 32767
IU2: 0 … 65535
In4: −8 … −1 or 1 … 8
In5: −16 … −1 or 1 … 16
In6: −32 … −1 or 1 … 32
IM2: −65536 … −1
Ilb: An 8 bit value with exactly one bit set.
Ilw: A 16 bit value with exactly one bit set.
Sd: The common src/dest memory addressing modes.
Sa: Memory addressed using $a0 or $a1.
Si: Memory addressed with immediate addresses.
Ss: Memory addressed using the stack pointer ($sp).
Sf: Memory addressed using the frame base register ($fb).
Ss: Memory addressed using the small base register ($sb).
S1: $r1h

LoongArch—config/loongarch/constraints.md

f: A floating-point or vector register (if available).
k: A memory operand whose address is formed by a base register and(optionally scaled) index register.
l: A signed 16-bit constant.
m: A memory operand whose address is formed by a base register and offsetthat is suitable for use in instructions with the same addressing modeasst.w andld.w.
q: A general-purpose register except for $r0 and $r1 (for the csrxchginstruction)
I: A signed 12-bit constant (for arithmetic instructions).
K: An unsigned 12-bit constant (for logic instructions).
M: A constant that cannot be loaded usinglui,addiuorori.
N: A constant in the range -65535 to -1 (inclusive).
O: A signed 15-bit constant.
P: A constant in the range 1 to 65535 (inclusive).
R: An address that can be used in a non-macro load or store.
ZB: An address that is held in a general-purpose register.The offset is zero.
ZC: A memory operand whose address is formed by a base register and offsetthat is suitable for use in instructions with the same addressing modeasll.w andsc.w.

MicroBlaze—config/microblaze/constraints.md

d: A general register (r0 tor31).
z: A status register (rmsr,$fcc1 to$fcc7).

MIPS—config/mips/constraints.md

d: A general-purpose register. This is equivalent tor unlessgenerating MIPS16 code, in which case the MIPS16 register set is used.
f: A floating-point register (if available).
h: Formerly thehi register. This constraint is no longer supported.
l: Thelo register. Use this register to store values that areno bigger than a word.
x: The concatenatedhi andlo registers. Use this registerto store doubleword values.
c: A register suitable for use in an indirect jump. This will always be$25 for-mabicalls.
v: Register$3. Do not use this constraint in new code;it is retained only for compatibility with glibc.
y: Equivalent tor; retained for backwards compatibility.
z: A floating-point condition code register.
I: A signed 16-bit constant (for arithmetic instructions).
J: Integer zero.
K: An unsigned 16-bit constant (for logic instructions).
L: A signed 32-bit constant in which the lower 16 bits are zero.Such constants can be loaded usinglui.
M: A constant that cannot be loaded usinglui,addiuorori.
N: A constant in the range −65535 to −1 (inclusive).
O: A signed 15-bit constant.
P: A constant in the range 1 to 65535 (inclusive).
G: Floating-point zero.
R: An address that can be used in a non-macro load or store.
ZC: A memory operand whose address is formed by a base register and offsetthat is suitable for use in instructions with the same addressing modeasll andsc.
ZD: An address suitable for aprefetch instruction, or for any otherinstruction with the same addressing mode asprefetch.

Motorola 680x0—config/m68k/constraints.md

a: Address register
d: Data register
f: 68881 floating-point register, if available
I: Integer in the range 1 to 8
J: 16-bit signed number
K: Signed number whose magnitude is greater than 0x80
L: Integer in the range −8 to −1
M: Signed number whose magnitude is greater than 0x100
N: Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
O: 16 (for rotate using swap)
P: Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
R: Numbers that mov3q can handle
G: Floating point constant that is not a 68881 constant
S: Operands that satisfy ’m’ when -mpcrel is in effect
T: Operands that satisfy ’s’ when -mpcrel is not in effect
Q: Address register indirect addressing mode
U: Register offset addressing
W: const_call_operand
Cs: symbol_ref or const
Ci: const_int
C0: const_int 0
Cj: Range of signed numbers that don’t fit in 16 bits
Cmvq: Integers valid for mvq
Capsw: Integers valid for a moveq followed by a swap
Cmvz: Integers valid for mvz
Cmvs: Integers valid for mvs
Ap: push_operand
Ac: Non-register operands allowed in clr

Moxie—config/moxie/constraints.md

A: An absolute address
B: An offset address
W: A register indirect memory operand
I: A constant in the range of 0 to 255.
N: A constant in the range of 0 to −255.

MSP430–config/msp430/constraints.md

R12: Register R12.
R13: Register R13.
K: Integer constant 1.
L: Integer constant -1^20..1^19.
M: Integer constant 1-4.
Ya: Memory references which do not require an extended MOVX instruction.
Yl: Memory reference, labels only.
Ys: Memory reference, stack only.

NDS32—config/nds32/constraints.md

w: LOW register class $r0 to $r7 constraint for V3/V3M ISA.
l: LOW register class $r0 to $r7.
d: MIDDLE register class $r0 to $r11, $r16 to $r19.
h: HIGH register class $r12 to $r14, $r20 to $r31.
t: Temporary assist register $ta (i.e. $r15).
k: Stack register $sp.
Iu03: Unsigned immediate 3-bit value.
In03: Negative immediate 3-bit value in the range of −7–0.
Iu04: Unsigned immediate 4-bit value.
Is05: Signed immediate 5-bit value.
Iu05: Unsigned immediate 5-bit value.
In05: Negative immediate 5-bit value in the range of −31–0.
Ip05: Unsigned immediate 5-bit value for movpi45 instruction with range 16–47.
Iu06: Unsigned immediate 6-bit value constraint for addri36.sp instruction.
Iu08: Unsigned immediate 8-bit value.
Iu09: Unsigned immediate 9-bit value.
Is10: Signed immediate 10-bit value.
Is11: Signed immediate 11-bit value.
Is15: Signed immediate 15-bit value.
Iu15: Unsigned immediate 15-bit value.
Ic15: A constant which is not in the range of imm15u but ok for bclr instruction.
Ie15: A constant which is not in the range of imm15u but ok for bset instruction.
It15: A constant which is not in the range of imm15u but ok for btgl instruction.
Ii15: A constant whose compliment value is in the range of imm15uand ok for bitci instruction.
Is16: Signed immediate 16-bit value.
Is17: Signed immediate 17-bit value.
Is19: Signed immediate 19-bit value.
Is20: Signed immediate 20-bit value.
Ihig: The immediate value that can be simply set high 20-bit.
Izeb: The immediate value 0xff.
Izeh: The immediate value 0xffff.
Ixls: The immediate value 0x01.
Ix11: The immediate value 0x7ff.
Ibms: The immediate value with power of 2.
Ifex: The immediate value with power of 2 minus 1.
U33: Memory constraint for 333 format.
U45: Memory constraint for 45 format.
U37: Memory constraint for 37 format.

OpenRISC—config/or1k/constraints.md

I: Integer that is valid as an immediate operand in aninstruction taking a signed 16-bit number. Range−32768 to 32767.
K: Integer that is valid as an immediate operand in aninstruction taking an unsigned 16-bit number. Range0 to 65535.
M: Signed 16-bit constant shifted left 16 bits. (Used withl.movhi)
O: Zero
c: Register usable for sibcalls.

PDP-11—config/pdp11/constraints.md

a: Floating point registers AC0 through AC3. These can be loaded from/tomemory with a single instruction.
d: Odd numbered general registers (R1, R3, R5). These are used for16-bit multiply operations.
D: A memory reference that is encoded within the opcode, but notauto-increment or auto-decrement.
f: Any of the floating point registers (AC0 through AC5).
G: Floating point constant 0.
h: Floating point registers AC4 and AC5. These cannot be loaded from/tomemory with a single instruction.
I: An integer constant that fits in 16 bits.
J: An integer constant whose low order 16 bits are zero.
K: An integer constant that does not meet the constraints for codes‘I’ or ‘J’.
L: The integer constant 1.
M: The integer constant −1.
N: The integer constant 0.
O: Integer constants 0 through 3; shifts by theseamounts are handled as multiple single-bit shifts rather than a singlevariable-length shift.
Q: A memory reference which requires an additional word (address oroffset) after the opcode.
R: A memory reference that is encoded within the opcode.

PowerPC and IBM RS6000—config/rs6000/constraints.md

r

A general purpose register (GPR),r0…r31.

b

A base register. Liker, butr0 is not allowed, sor1…r31.

f

A floating point register (FPR),f0…f31.

d

A floating point register. This is the same asf nowadays;historicallyf was for single-precision andd was fordouble-precision floating point.

v

An Altivec vector register (VR),v0…v31.

wa

A VSX register (VSR),vs0…vs63. This is either anFPR (vs0…vs31 aref0…f31) or a VR(vs32…vs63 arev0…v31).

When usingwa, you should use the%x output modifier, so thatthe correct register number is printed. For example:

asm ("xvadddp %x0,%x1,%x2"     : "=wa" (v1)     : "wa" (v2), "wa" (v3));

You should not use%x forv operands:

asm ("xsaddqp %0,%1,%2"     : "=v" (v1)     : "v" (v2), "v" (v3));

h

A special register (vrsave,ctr, orlr).

c

The count register,ctr.

l

The link register,lr.

x

Condition register field 0,cr0.

y

Any condition register field,cr0…cr7.

z

The carry bit,XER[CA].

we

Likewa, if this is a POWER9 or later and-mvsxand-m64 are used; otherwise,NO_REGS.

wn

No register (NO_REGS).

wr

Liker, if-mpowerpc64 is used; otherwise,NO_REGS.

wx

Liked, if-mpowerpc-gfxopt is used; otherwise,NO_REGS.

wA

Likeb, if-mpowerpc64 is used; otherwise,NO_REGS.

wB

Signed 5-bit constant integer that can be loaded into an Altivec register.

wE

Vector constant that can be loaded with the XXSPLTIB instruction.

wF

Memory operand suitable for power8 GPR load fusion.

wL

Int constant that is the element number mfvsrld accesses in a vector.

wM

Match vector constant with all 1’s if the XXLORC instruction is available.

wO

Memory operand suitable for the ISA 3.0 vector d-form instructions.

wQ

Memory operand suitable for the load/store quad instructions.

wS

Vector constant that can be loaded with XXSPLTIB & sign extension.

wY

A memory operand for a DS-form instruction.

wZ

An indexed or indirect memory operand, ignoring the bottom 4 bits.

I

A signed 16-bit constant.

J

An unsigned 16-bit constant shifted left 16 bits (useL insteadforSImode constants).

K

An unsigned 16-bit constant.

L

A signed 16-bit constant shifted left 16 bits.

M

An integer constant greater than 31.

N

An exact power of 2.

O

The integer constant zero.

P

A constant whose negation is a signed 16-bit constant.

eI

A signed 34-bit integer constant if prefixed instructions are supported.

eP

A scalar floating point constant or a vector constant that can beloaded to a VSX register with one prefixed instruction.

eQ

An IEEE 128-bit constant that can be loaded into a VSX register withthelxvkq instruction.

G

A floating point constant that can be loaded into a register with oneinstruction per word.

H

A floating point constant that can be loaded into a register usingthree instructions.

m

A memory operand.Normally,m does not allow addresses that update the base register.If the< or> constraint is also used, they are allowed andtherefore on PowerPC targets in that case it is only safeto usem<> in anasm statement if thatasm statementaccesses the operand exactly once. Theasm statement must alsouse%U<opno> as a placeholder for the “update” flag in thecorresponding load or store instruction. For example:

asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));

is correct but:

asm ("st %1,%0" : "=m<>" (mem) : "r" (val));

is not.

es

A “stable” memory operand; that is, one which does not include anyautomodification of the base register. This used to be useful whenm allowed automodification of the base register, but as thoseare now only allowed when< or> is used,es isbasically the same asm without< and>.

Q

A memory operand addressed by just a base register.

Y

A memory operand for a DQ-form instruction.

Z

A memory operand accessed with indexed or indirect addressing.

R

An AIX TOC entry.

a

An indexed or indirect address.

U

A V.4 small data reference.

W

A vector constant that does not require memory.

j

The zero vector constant.

PRU—config/pru/constraints.md

I: An unsigned 8-bit integer constant.
J: An unsigned 16-bit integer constant.
L: An unsigned 5-bit integer constant (for shift counts).
T: A text segment (program memory) constant label.
Z: Integer constant zero.

RL78—config/rl78/constraints.md

Int3: An integer constant in the range 1 … 7.
Int8: An integer constant in the range 0 … 255.
J: An integer constant in the range −255 … 0
K: The integer constant 1.
L: The integer constant -1.
M: The integer constant 0.
N: The integer constant 2.
O: The integer constant -2.
P: An integer constant in the range 1 … 15.
Qbi: The built-in compare types–eq, ne, gtu, ltu, geu, and leu.
Qsc: The synthetic compare types–gt, lt, ge, and le.
Wab: A memory reference with an absolute address.
Wbc: A memory reference usingBC as a base register, with an optional offset.
Wca: A memory reference usingAX,BC,DE, orHL for the address, for calls.
Wcv: A memory reference using any 16-bit register pair for the address, for calls.
Wd2: A memory reference usingDE as a base register, with an optional offset.
Wde: A memory reference usingDE as a base register, without any offset.
Wfr: Any memory reference to an address in the far address space.
Wh1: A memory reference usingHL as a base register, with an optional one-byte offset.
Whb: A memory reference usingHL as a base register, withB orC as the index register.
Whl: A memory reference usingHL as a base register, without any offset.
Ws1: A memory reference usingSP as a base register, with an optional one-byte offset.
Y: Any memory reference to an address in the near address space.
A: TheAX register.
B: TheBC register.
D: TheDE register.
R: A throughL registers.
S: TheSP register.
T: TheHL register.
Z08W: The 16-bitR8 register.
Z10W: The 16-bitR10 register.
Zint: The registers reserved for interrupts (R24 toR31).
a: TheA register.
b: TheB register.
c: TheC register.
d: TheD register.
e: TheE register.
h: TheH register.
l: TheL register.
v: The virtual registers.
w: ThePSW register.
x: TheX register.

RISC-V—config/riscv/constraints.md

f: A floating-point register (if available).
I: An I-type 12-bit signed immediate.
J: Integer zero.
K: A 5-bit unsigned immediate for CSR access instructions.
A: An address that is held in a general-purpose register.
S: A constraint that matches an absolute symbolic address.
vr: A vector register (if available)..
vd: A vector register, excluding v0 (if available).
vm: A vector register, only v0 (if available).
cr: RVC general purpose register (x8-x15).
cf: RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when usezfinx.
cR: Even-odd RVC general purpose register pair.
R: Even-odd general purpose register pair.

RX—config/rx/constraints.md

Q: An address which does not involve register indirect addressing orpre/post increment/decrement addressing.
Symbol: A symbol reference.
Int08: A constant in the range −256 to 255, inclusive.
Sint08: A constant in the range −128 to 127, inclusive.
Sint16: A constant in the range −32768 to 32767, inclusive.
Sint24: A constant in the range −8388608 to 8388607, inclusive.
Uint04: A constant in the range 0 to 15, inclusive.

S/390 and zSeries—config/s390/s390.h

a

Address register (general purpose register except r0)

c

Condition code register

d

Data register (arbitrary general purpose register)

f

Floating-point register

I

Unsigned 8-bit constant (0–255)

J

Unsigned 12-bit constant (0–4095)

K

Signed 16-bit constant (−32768–32767)

L

Value appropriate as displacement.

(0..4095): for short displacement
(−524288..524287): for long displacement

M

Constant integer with a value of 0x7fffffff.

N

Multiple letter constraint followed by 4 parameter letters.

0..9:: number of the part counting from most to least significant
H,Q:: mode of the part
D,S,H:: mode of the containing operand
0,F:: value of the other parts (F—all bits set)

The constraint matches if the specified part of a constanthas a value different from its other parts.

Q

Memory reference without index register and with short displacement.

R

Memory reference with index register and short displacement.

S

Memory reference without index register but with long displacement.

T

Memory reference with index register and long displacement.

U

Pointer with short displacement.

W

Pointer with long displacement.

Y

Shift count operand.

SPARC—config/sparc/sparc.h

f: Floating-point register on the SPARC-V8 architecture andlower floating-point register on the SPARC-V9 architecture.
e: Floating-point register. It is equivalent to ‘f’ on theSPARC-V8 architecture and contains both lower and upperfloating-point registers on the SPARC-V9 architecture.
c: Floating-point condition code register.
d: Lower floating-point register. It is only valid on the SPARC-V9architecture when the Visual Instruction Set is available.
b: Floating-point register. It is only valid on the SPARC-V9 architecturewhen the Visual Instruction Set is available.
h: 64-bit global or out register for the SPARC-V8+ architecture.
C: The constant all-ones, for floating-point.
A: Signed 5-bit constant
D: A vector constant
I: Signed 13-bit constant
J: Zero
K: 32-bit constant with the low 12 bits clear (a constant that can beloaded with thesethi instruction)
L: A constant in the range supported bymovcc instructions (11-bitsigned immediate)
M: A constant in the range supported bymovrcc instructions (10-bitsigned immediate)
N: Same as ‘K’, except that it verifies that bits that are not in thelower 32-bit range are all zero. Must be used instead of ‘K’ formodes wider thanSImode
O: The constant 4096
G: Floating-point zero
H: Signed 13-bit constant, sign-extended to 32 or 64 bits
P: The constant -1
Q: Floating-point constant whose integral representation canbe moved into an integer register using a single sethiinstruction
R: Floating-point constant whose integral representation canbe moved into an integer register using a single movinstruction
S: Floating-point constant whose integral representation canbe moved into an integer register using a high/lo_suminstruction sequence
T: Memory address aligned to an 8-byte boundary
W: Memory address for ‘e’ constraint registers
w: Memory address with only a base register
Y: Vector zero

TI C6X family—config/c6x/constraints.md

a: Register file A (A0–A31).
b: Register file B (B0–B31).
A: Predicate registers in register file A (A0–A2 on C64X andhigher, A1 and A2 otherwise).
B: Predicate registers in register file B (B0–B2).
C: A call-used register in register file B (B0–B9, B16–B31).
Da: Register file A, excluding predicate registers (A3–A31,plus A0 if not C64X or higher).
Db: Register file B, excluding predicate registers (B3–B31).
Iu4: Integer constant in the range 0 … 15.
Iu5: Integer constant in the range 0 … 31.
In5: Integer constant in the range −31 … 0.
Is5: Integer constant in the range −16 … 15.
I5x: Integer constant that can be the operand of an ADDA or a SUBA insn.
IuB: Integer constant in the range 0 … 65535.
IsB: Integer constant in the range −32768 … 32767.
IsC: Integer constant in the range-2^{20} …2^{20} - 1.
Jc: Integer constant that is a valid mask for the clr instruction.
Js: Integer constant that is a valid mask for the set instruction.
Q: Memory location with A base register.
R: Memory location with B base register.
S0: On C64x+ targets, a GP-relative small data reference.
S1: Any kind ofSYMBOL_REF, for use in a call address.
Si: Any kind of immediate operand, unless it matches the S0 constraint.
T: Memory location with B base register, but not using a long offset.
W: A memory operand with an address that cannot be used in an unaligned access.
Z: Register B14 (aka DP).

Visium—config/visium/constraints.md

b: EAM registermdb
c: EAM registermdc
f: Floating point register
k: Register for sibcall optimization
l: General register, but notr29,r30 andr31
t: Registerr1
u: Registerr2
v: Registerr3
G: Floating-point constant 0.0
J: Integer constant in the range 0 .. 65535 (16-bit immediate)
K: Integer constant in the range 1 .. 31 (5-bit immediate)
L: Integer constant in the range −65535 .. −1 (16-bit negative immediate)
M: Integer constant −1
O: Integer constant 0
P: Integer constant 32

x86 family—config/i386/constraints.md

R

Legacy register—the eight integer registers available on alli386 processors (a,b,c,d,si,di,bp,sp).

q

Any register accessible asrl. In 32-bit mode,a,b,c, andd; in 64-bit mode, any integer register.

Q

Any register accessible asrh:a,b,c, andd.

l

Any register that can be used as the index in a base+index memoryaccess: that is, any general register except the stack pointer.

a

Thea register.

b

Theb register.

c

Thec register.

d

Thed register.

S

Thesi register.

D

Thedi register.

A

Thea andd registers. This class is used for instructionsthat return double word results in theax:dx register pair. Singleword values will be allocated either inax ordx.For example on i386 the following implementsrdtsc:

unsigned long long rdtsc (void){  unsigned long long tick;  __asm__ __volatile__("rdtsc":"=A"(tick));  return tick;}

This is not correct on x86-64 as it would allocate tick in eitheraxordx. You have to use the following variant instead:

unsigned long long rdtsc (void){  unsigned int tickl, tickh;  __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));  return ((unsigned long long)tickh << 32)|tickl;}

U

The call-clobbered integer registers.

f

Any 80387 floating-point (stack) register.

t

Top of 80387 floating-point stack (%st(0)).

u

Second from top of 80387 floating-point stack (%st(1)).

Yk

Any mask register that can be used as a predicate, i.e.k1-k7.

k

Any mask register.

y

Any MMX register.

x

Any SSE register.

v

Any EVEX encodable SSE register (%xmm0-%xmm31).

w

Any bound register.

Yz

First SSE register (%xmm0).

Yi

Any SSE register, when SSE2 and inter-unit moves are enabled.

Yj

Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.

Ym

Any MMX register, when inter-unit moves are enabled.

Yn

Any MMX register, when inter-unit moves from vector registers are enabled.

Yp

Any integer register whenTARGET_PARTIAL_REG_STALL is disabled.

Ya

Any integer register when zero extensions withAND are disabled.

Yb

Any register that can be used as the GOT base when calling
___tls_get_addr: that is, any general register exceptaandsp registers, for-fno-plt if linker supports it.Otherwise,b register.

Yf

Any x87 register when 80387 floating-point arithmetic is enabled.

Yr

Lower SSE register when avoiding REX prefix and all SSE registers otherwise.

Yv

For AVX512VL, any EVEX-encodable SSE register (%xmm0-%xmm31),otherwise any SSE register.

Yh

Any EVEX-encodable SSE register, that has number factor of four.

Bf

Flags register operand.

Bg

GOT memory operand.

Bm

Vector memory operand.

Bc

Constant memory operand.

Bn

Memory operand without REX prefix.

Bs

Sibcall memory operand.

Bw

Call memory operand.

Bz

Constant call address operand.

BC

SSE constant -1 operand.

I

Integer constant in the range 0 … 31, for 32-bit shifts.

J

Integer constant in the range 0 … 63, for 64-bit shifts.

K

Signed 8-bit integer constant.

L

0xFF or0xFFFF, for andsi as a zero-extending move.

M

0, 1, 2, or 3 (shifts for thelea instruction).

N

Unsigned 8-bit integer constant (forin andoutinstructions).

O

Integer constant in the range 0 … 127, for 128-bit shifts.

G

Standard 80387 floating point constant.

C

SSE constant zero operand.

e

32-bit signed integer constant, or a symbolic reference knownto fit that range (for immediate operands in sign-extending x86-64instructions).

We

32-bit signed integer constant, or a symbolic reference knownto fit that range (for sign-extending conversion operations thatrequire non-VOIDmode immediate operands).

Wz

32-bit unsigned integer constant, or a symbolic reference knownto fit that range (for zero-extending conversion operations thatrequire non-VOIDmode immediate operands).

Wd

128-bit integer constant where both the high and low 64-bit wordsatisfy thee constraint.

Ws

A symbolic reference or label reference.You can use the%p modifier to print the raw symbol.

Z

32-bit unsigned integer constant, or a symbolic reference knownto fit that range (for immediate operands in zero-extending x86-64instructions).

Tv

VSIB address operand.

Ts

Address operand without segment register.

Xstormy16—config/stormy16/stormy16.h

a: Register r0.
b: Register r1.
c: Register r2.
d: Register r8.
e: Registers r0 through r7.
t: Registers r0 and r1.
y: The carry register.
z: Registers r8 and r9.
I: A constant between 0 and 3 inclusive.
J: A constant that has exactly one bit set.
K: A constant that has exactly one bit clear.
L: A constant between 0 and 255 inclusive.
M: A constant between −255 and 0 inclusive.
N: A constant between −3 and 0 inclusive.
O: A constant between 1 and 4 inclusive.
P: A constant between −4 and −1 inclusive.
Q: A memory reference that is a stack push.
R: A memory reference that is a stack pop.
S: A memory reference that refers to a constant address of known value.
T: The register indicated by Rx (not implemented yet).
U: A constant that is not between 2 and 15 inclusive.
Z: The constant 0.

Xtensa—config/xtensa/constraints.md

a: General-purpose 32-bit register
b: One-bit boolean register
A: MAC16 40-bit accumulator register
I: Signed 12-bit integer constant, for use in MOVI instructions
J: Signed 8-bit integer constant, for use in ADDI instructions
K: Integer constant valid for BccI instructions
L: Unsigned constant valid for BccUI instructions