Next:Parameters for Precompiled Header Validity Checking, Previous:Emulating TLS, Up:Target Description Macros and Functions [Contents][Index]
The MIPS specification allows MIPS implementations to have as many as 4coprocessors, each with as many as 32 private registers. GCC supportsaccessing these registers and transferring values between the registersand memory using asm-ized variables. For example:
register unsigned int cp0count asm ("c0r1"); unsigned int d; d = cp0count + 3;(“c0r1” is the default name of register 1 in coprocessor 0; alternatenames may be added as described below, or the default names may beoverridden entirely inSUBTARGET_CONDITIONAL_REGISTER_USAGE.)
Coprocessor registers are assumed to be epilogue-used; sets to them willbe preserved even if it does not appear that the register is used againlater in the function.
Another note: according to the MIPS spec, coprocessor 1 (if present) isthe FPU. One accesses COP1 registers through standard mipsfloating-point support; they are not included in this mechanism.