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These ‘-m’ options are defined for the x86 family of computers.
-march=cpu-type ¶Generate instructions for the machine typecpu-type. In contrast to-mtune=cpu-type, which merely tunes the generated codefor the specifiedcpu-type,-march=cpu-type allows GCCto generate code that may not run at all on processors other than the oneindicated. Specifying-march=cpu-type implies-mtune=cpu-type, except where noted otherwise.
The choices forcpu-type are:
This selects the CPU to generate code for at compilation time by determiningthe processor type of the compiling machine. Using-march=nativeenables all instruction subsets supported by the local machine (hencethe result might not run on different machines). Using-mtune=nativeproduces code optimized for the local machine under the constraintsof the selected instruction set.
A generic CPU with 64-bit extensions, MMX, SSE, SSE2, and FXSR instruction setsupport.
These choices forcpu-type select the correspondingmicro-architecture level from the x86-64 psABI. On ABIs other thanthe x86-64 psABI they select the same CPU features as the x86-64 psABIdocuments for the particular micro-architecture level.
Since thesecpu-type values do not have a corresponding-mtune setting, using-march with these values enablesgeneric tuning. Specific tuning can be enabled using the-mtune=other-cpu-type option with an appropriateother-cpu-type value.
Original Intel i386 CPU.
Intel i486 CPU. (No scheduling is implemented for this chip.)
Intel Pentium CPU with no MMX support.
Intel Lakemont MCU, based on Intel Pentium CPU.
Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.
Intel Pentium Pro CPU with no MMX support.
When used with-march, the Pentium Proinstruction set is used, so the code runs on all i686 family chips.When used with-mtune, it has the same meaning as ‘generic’.
Intel Pentium II CPU, based on Pentium Pro core with MMX and FXSR instructionset support.
Intel Pentium III CPU, based on Pentium Pro core with MMX, FXSR and SSEinstruction set support.
Intel Pentium M; low-power version of Intel Pentium III CPUwith MMX, SSE, SSE2 and FXSR instruction set support. Used by Centrinonotebooks.
Intel Pentium 4 CPU with MMX, SSE, SSE2 and FXSR instruction set support.
Improved version of Intel Pentium 4 CPU with MMX, SSE, SSE2, SSE3 and FXSRinstruction set support.
Improved version of Intel Pentium 4 CPU with 64-bit extensions, MMX, SSE,SSE2, SSE3 and FXSR instruction set support.
Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, CX16,SAHF and FXSR instruction set support.
Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF and FXSR instruction set support.
Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR and PCLMUL instruction set support.
Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE and PCLMUL instruction setsupport.
Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRNDand F16C instruction set support.
Intel Haswell CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE and HLE instruction set support.
Intel Broadwell CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX and PREFETCHWinstruction set support.
Intel Skylake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,CLFLUSHOPT, XSAVEC, XSAVES and SGX instruction set support.
Intel Skylake Server CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, CLWB, AVX512VL, AVX512BW,AVX512DQ and AVX512CD instruction set support.
Intel Cascade Lake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ,AVX512CD and AVX512VNNI instruction set support.
Intel Cannon Lake Server CPU with 64-bit extensions, MMX, SSE, SSE2,SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL,FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX,PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW,AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA and SHA instruction setsupport.
Intel Cooper Lake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ,AVX512CD, AVX512VNNI and AVX512BF16 instruction set support.
Intel Ice Lake Client CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID and AVX512VPOPCNTDQ instruction set support.
Intel Ice Lake Server CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD and CLWBinstruction set support.
Intel Tiger Lake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CDPKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, MOVDIRI, MOVDIR64B, CLWB,AVX512VP2INTERSECT and KEYLOCKER instruction set support.
Intel Rocket Lake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CDPKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,VPCLMULQDQ, AVX512BITALG, RDPID and AVX512VPOPCNTDQ instruction set support.
Intel Alder Lake/Raptor Lake/Meteor Lake/Gracemont CPU with 64-bit extensions,MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW,PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX,GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C,FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL andAVX-VNNI instruction set support.
Intel Arrow Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU,VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA,AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support.
Intel Arrow Lake S/Lunar Lake CPU with 64-bit extensions, MOVBE, MMX, SSE,SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND,XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB,MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR,AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3 andSM4 instruction set support.
Intel Panther Lake/Wildcat Lake CPU with 64-bit extensions, MOVBE, MMX, SSE,SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND,XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE,CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA,LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR,AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3 andSM4 instruction set support.
Intel Nova Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU,VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8,AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and PREFETCHIinstruction set support.
Intel Sapphire Rapids/Emerald Rapids CPU with 64-bit extensions, MMX, SSE,SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL,FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX,PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW,AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES,AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG,WBNOINVD, CLWB, MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512-FP16and AVX512BF16 instruction set support.
Intel Granite Rapids CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB,MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK,UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512-FP16, AVX512BF16, AMX-FP16and PREFETCHI instruction set support.
Intel Granite Rapids D CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB,MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK,UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16,PREFETCHI and AMX-COMPLEX instruction set support.
Intel Diamond Rapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB,MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK,UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16,PREFETCHI, AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16,AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512,AMX-FP8, AMX-TF32, MOVRS and AMX-MOVRS instruction set support.
Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3instruction set support.
Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW and RDRNDinstruction set support.
Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW, RDRND, AES, SHA,RDSEED, XSAVE, XSAVEC, XSAVES, XSAVEOPT, CLFLUSHOPT and FSGSBASE instructionset support.
Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW, RDRND, AES,SHA, RDSEED, XSAVE, XSAVEC, XSAVES, XSAVEOPT, CLFLUSHOPT, FSGSBASE, PTWRITE,RDPID and SGX instruction set support.
Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW, RDRND, AES, SHA,RDSEED, XSAVE, XSAVEC, XSAVES, XSAVEOPT, CLFLUSHOPT, FSGSBASE, PTWRITE, RDPID,SGX, CLWB, GFNI-SSE, MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG instruction setsupport.
Intel Sierra Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and UINTR instruction setsupport.
Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and UINTR instruction setsupport.
Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE,XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB,MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA,LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, ENQCMD,UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512,SM3, SM4, USER_MSR and PREFETCHI instruction set support.
AMD K6 CPU with MMX instruction set support.
Improved versions of AMD K6 CPU with MMX and 3DNow! instruction set support.
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow! and SSE prefetch instructionssupport.
Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow! and full SSEinstruction set support.
Processors based on the AMD K8 core with x86-64 instruction set support,including the AMD Opteron, Athlon 64, and Athlon 64 FX processors.(This supersets MMX, SSE, SSE2, 3DNow!, enhanced 3DNow! and 64-bitinstruction set extensions.)
Improved versions of AMD K8 cores with SSE3 instruction set support.
CPUs based on AMD Family 10h cores with x86-64 instruction set support. (Thissupersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bitinstruction set extensions.)
CPUs based on AMD Family 15h cores with x86-64 instruction set support. (Thissupersets FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
AMD Family 15h core based CPUs with x86-64 instruction set support. (Thissupersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX,SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction setextensions.)
AMD Family 15h core based CPUs with x86-64 instruction set support. (Thissupersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES,PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and64-bit instruction set extensions.)
AMD Family 15h core based CPUs with x86-64 instruction set support. (Thissupersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP,AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,SSE4.2, ABM and 64-bit instruction set extensions.)
AMD Family 17h core based CPUs with x86-64 instruction set support. (Thissupersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX,SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3,SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bitinstruction set extensions.)
AMD Family 17h core based CPUs with x86-64 instruction set support. (Thissupersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID,WBNOINVD, and 64-bit instruction set extensions.)
AMD Family 19h core based CPUs with x86-64 instruction set support. (Thissupersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID,WBNOINVD, PKU, VPCLMULQDQ, VAES, and 64-bit instruction set extensions.)
AMD Family 19h core based CPUs with x86-64 instruction set support. (Thissupersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID,WBNOINVD, PKU, VPCLMULQDQ, VAES, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, AVX512VNNI,AVX512BITALG, AVX512VPOPCNTDQ, GFNI and 64-bit instruction set extensions.)
AMD Family 1ah core based CPUs with x86-64 instruction set support. (Thissupersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID,WBNOINVD, PKU, VPCLMULQDQ, VAES, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, AVX512VNNI,AVX512BITALG, AVX512VPOPCNTDQ, GFNI, AVXVNNI, MOVDIRI, MOVDIR64B,AVX512VP2INTERSECT, PREFETCHI and 64-bit instruction set extensions.)
CPUs based on AMD Family 14h cores with x86-64 instruction set support. (Thissupersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bitinstruction set extensions.)
CPUs based on AMD Family 16h cores with x86-64 instruction set support. Thisincludes MOVBE, F16C, BMI, AVX, PCLMUL, AES, SSE4.2, SSE4.1, CX16, ABM,SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.
IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instructionset support.
IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow!instruction set support.
VIA C3 CPU with MMX and 3DNow! instruction set support.(No scheduling is implemented for this chip.)
VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support.(No scheduling is implemented for this chip.)
VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support.(No scheduling is implemented for this chip.)
VIA Eden Samuel 2 CPU with MMX and 3DNow! instruction set support.(No scheduling is implemented for this chip.)
VIA Eden Nehemiah CPU with MMX and SSE instruction set support.(No scheduling is implemented for this chip.)
VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support.(No scheduling is implemented for this chip.)
VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support.(No scheduling is implemented for this chip.)
VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2,AVX and AVX2 instruction set support.(No scheduling is implemented for this chip.)
Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3instruction set support.(No scheduling is implemented for this chip.)
VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3instruction set support.(No scheduling is implemented for this chip.)
VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3instruction set support.(No scheduling is implemented for this chip.)
VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1instruction set support.(No scheduling is implemented for this chip.)
VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1instruction set support.(No scheduling is implemented for this chip.)
VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1instruction set support.(No scheduling is implemented for this chip.)
ZHAOXIN lujiazui CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16,ABM, BMI, BMI2, FXSR, RDSEED instruction set support. While the CPUsdo support AVX and F16C, these aren’t enabled by-march=lujiazuifor performance reasons.
ZHAOXIN yongfeng CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16,ABM, BMI, BMI2, F16C, FXSR, RDSEED, AVX2, FMA, SHA, LZCNTinstruction set support.
ZHAOXIN shijidadao CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16,ABM, BMI, BMI2, F16C, FXSR, RDSEED, AVX2, FMA, SHA, LZCNTinstruction set support.
AMD Geode embedded processor with MMX and 3DNow! instruction set support.
-mtune=cpu-type ¶Tune tocpu-type everything applicable about the generated code, exceptfor the ABI and the set of available instructions.While picking a specificcpu-type schedules things appropriatelyfor that particular chip, the compiler does not generate any code thatcannot run on the default machine type unless you use a-march=cpu-type option.For example, if GCC is configured for i686-pc-linux-gnuthen-mtune=pentium4 generates code that is tuned for Pentium 4but still runs on i686 machines.
The choices forcpu-type are the same as for-march.In addition,-mtune supports 2 extra choices forcpu-type:
Produce code optimized for the most common IA32/AMD64/EM64T processors.If you know the CPU on which your code will run, then you should usethe corresponding-mtune or-march option instead of-mtune=generic. But, if you do not know exactly what CPU usersof your application will have, then you should use this option.
As new processors are deployed in the marketplace, the behavior of thisoption will change. Therefore, if you upgrade to a newer version ofGCC, code generation controlled by this option will change to reflectthe processorsthat are most common at the time that version of GCC is released.
There is no-march=generic option because-marchindicates the instruction set the compiler can use, and there is nogeneric instruction set applicable to all processors. In contrast,-mtune indicates the processor (or, in this case, collection ofprocessors) for which the code is optimized.
Produce code optimized for the most current Intel processors, which areHaswell and Silvermont for this version of GCC. If you know the CPUon which your code will run, then you should use the corresponding-mtune or-march option instead of-mtune=intel.But, if you want your application performs better on both Diamond Rapidsand Clearwater Forest, then you should use this option.
As new Intel processors are deployed in the marketplace, the behavior ofthis option will change. Therefore, if you upgrade to a newer version ofGCC, code generation controlled by this option will change to reflectthe most current Intel processors at the time that version of GCC isreleased.
There is no-march=intel option because-march indicatesthe instruction set the compiler can use, and there is no commoninstruction set applicable to all processors. In contrast,-mtune indicates the processor (or, in this case, collection ofprocessors) for which the code is optimized.
-mcpu=cpu-type ¶A deprecated synonym for-mtune.
-mfpmath=unit ¶Generate floating-point arithmetic for selected unitunit. The choicesforunit are:
Use the standard 387 floating-point coprocessor present on the majority of chips andemulated otherwise. Code compiled with this option runs almost everywhere.The temporary results are computed in 80-bit precision instead of the precisionspecified by the type, resulting in slightly different results compared to mostof other chips. See-ffloat-store for more detailed description.
This is the default choice for non-Darwin x86-32 targets.
Use scalar floating-point instructions present in the SSE instruction set.This instruction set is supported by Pentium III and newer chips,and in the AMD lineby Athlon-4, Athlon XP and Athlon MP chips. The earlier version of the SSEinstruction set supports only single-precision arithmetic, thus the double andextended-precision arithmetic are still done using 387. A later version, presentonly in Pentium 4 and AMD x86-64 chips, supports double-precisionarithmetic too.
For the x86-32 compiler, you must use-march=cpu-type,-msseor-msse2 switches to enable SSE extensions and make this optioneffective. For the x86-64 compiler, these extensions are enabled by default.
The resulting code should be considerably faster in the majority of cases and avoidthe numerical instability problems of 387 code, but may break some existingcode that expects temporaries to be 80 bits.
This is the default choice for the x86-64 compiler, Darwin x86-32 targets,and the default choice for x86-32 targets with the SSE2 instruction setwhen-ffast-math is enabled.
Attempt to utilize both instruction sets at once. This effectively doubles theamount of available registers, and on chips with separate execution units for387 and SSE the execution resources too. Use this option with care, as it isstill experimental, because the GCC register allocator does not model separatefunctional units well, resulting in unstable performance.
-masm=dialect ¶Output assembly instructions using selecteddialect. Also affectswhich dialect is used for basicasm (seeBasic Asm — Assembler Instructions Without Operands) andextendedasm (seeExtended Asm - Assembler Instructions with C Expression Operands). Supported choices (in dialectorder) are ‘att’ or ‘intel’. The default is ‘att’. Darwin doesnot support ‘intel’.
-mieee-fp ¶-mno-ieee-fpControl whether or not the compiler uses IEEE floating-pointcomparisons. These correctly handle the case where the result of acomparison is unordered.
-m80387 ¶-mhard-floatGenerate output containing 80387 instructions for floating point.
-mno-80387 ¶-msoft-floatGenerate output containing library calls for floating point.
Warning: the requisite libraries are not part of GCC.Normally the facilities of the machine’s usual C compiler are used, butthis cannot be done directly in cross-compilation. You must make yourown arrangements to provide suitable library functions forcross-compilation.
On machines where a function returns floating-point results in the 80387register stack, some floating-point opcodes may be emitted even if-msoft-float is used.
-mno-fp-ret-in-387 ¶Do not use the FPU registers for return values of functions.
The usual calling convention has functions return values of typesfloat anddouble in an FPU register, even if thereis no FPU. The idea is that the operating system should emulatean FPU.
The option-mno-fp-ret-in-387 causes such values to be returnedin ordinary CPU registers instead.
-mno-fancy-math-387 ¶Some 387 emulators do not support thesin,cos andsqrt instructions for the 387. Specify this option to avoidgenerating those instructions.This option is overridden when-marchindicates that the target CPU always has an FPU and so theinstruction does not need emulation. Theseinstructions are not generated unless you also use the-funsafe-math-optimizations switch.
-malign-double ¶-mno-align-doubleControl whether GCC alignsdouble,long double, andlong long variables on a two-word boundary or a one-wordboundary. Aligningdouble variables on a two-word boundaryproduces code that runs somewhat faster on a Pentium at theexpense of more memory.
On x86-64,-malign-double is enabled by default.
Warning: if you use the-malign-double switch,structures containing the above types are aligned differently thanthe published application binary interface specifications for the x86-32and are not binary compatible with structures in code compiledwithout that switch.
-m96bit-long-double ¶-m128bit-long-doubleThese switches control the size oflong double type. The x86-32application binary interface specifies the size to be 96 bits,so-m96bit-long-double is the default in 32-bit mode.
Modern architectures (Pentium and newer) preferlong doubleto be aligned to an 8- or 16-byte boundary. In arrays or structuresconforming to the ABI, this is not possible. So specifying-m128bit-long-double alignslong doubleto a 16-byte boundary by padding thelong double with an additional32-bit zero.
In the x86-64 compiler,-m128bit-long-double is the default choice asits ABI specifies thatlong double is aligned on 16-byte boundary.
Notice that neither of these options enable any extra precision over the x87standard of 80 bits for along double.
Warning: if you override the default value for your target ABI, thischanges the size ofstructures and arrays containinglong double variables,as well as modifying the function calling convention for functions takinglong double. Hence they are not binary-compatiblewith code compiled without that switch.
-mlong-double-64 ¶-mlong-double-80-mlong-double-128These switches control the size oflong double type. A sizeof 64 bits makes thelong double type equivalent to thedoubletype. This is the default for 32-bit Bionic C library. A sizeof 128 bits makes thelong double type equivalent to the__float128 type. This is the default for 64-bit Bionic C library.
Warning: if you override the default value for your target ABI, thischanges the size ofstructures and arrays containinglong double variables,as well as modifying the function calling convention for functions takinglong double. Hence they are not binary-compatiblewith code compiled without that switch.
-malign-data=type ¶Control how GCC aligns variables. Supported values fortype are‘compat’ uses increased alignment value compatible uses GCC 4.8and earlier, ‘abi’ uses alignment value as specified by thepsABI, and ‘cacheline’ uses increased alignment value to matchthe cache line size. ‘compat’ is the default.
-mlarge-data-threshold=threshold ¶When-mcmodel=medium or-mcmodel=large is specified, dataobjects larger thanthreshold are placed in large data sections. Thedefault is 65535.
-mrtd ¶Use a different function-calling convention, in which functions thattake a fixed number of arguments return with theretnuminstruction, which pops their arguments while returning. This saves oneinstruction in the caller since there is no need to pop the argumentsthere.
You can specify that an individual function is called with this callingsequence with the function attributestdcall. You can alsooverride the-mrtd option by using the function attributecdecl. SeeDeclaring Attributes of Functions.
Warning: this calling convention is incompatible with the onenormally used on Unix, so you cannot use it if you need to calllibraries compiled with the Unix compiler.
Also, you must provide function prototypes for all functions thattake variable numbers of arguments (includingprintf);otherwise incorrect code is generated for calls to thosefunctions.
In addition, seriously incorrect code results if you call afunction with too many arguments. (Normally, extra arguments areharmlessly ignored.)
-mregparm=num ¶Control how many registers are used to pass integer arguments. Bydefault, no registers are used to pass arguments, and at most 3registers can be used. You can control this behavior for a specificfunction by using the function attributeregparm.SeeDeclaring Attributes of Functions.
Warning: if you use this switch, andnum is nonzero, then you must build all modules with the samevalue, including any libraries. This includes the system libraries andstartup modules.
-msseregparm ¶Use SSE register passing conventions for float and double argumentsand return values. You can control this behavior for a specificfunction by using the function attributesseregparm.SeeDeclaring Attributes of Functions.
Warning: if you use this switch then you must build allmodules with the same value, including any libraries. This includesthe system libraries and startup modules.
-mvect8-ret-in-mem ¶Return 8-byte vectors in memory instead of MMX registers. This is thedefault on VxWorks to match the ABI of the Sun Studio compilers untilversion 12.Only use this option if you need to remaincompatible with existing code produced by those previous compilerversions or older versions of GCC.
-mpc32 ¶-mpc64-mpc80Set 80387 floating-point precision to 32, 64 or 80 bits. When-mpc32is specified, the significands of results of floating-point operations arerounded to 24 bits (single precision);-mpc64 rounds thesignificands of results of floating-point operations to 53 bits (doubleprecision) and-mpc80 rounds the significands of results offloating-point operations to 64 bits (extended double precision), which isthe default. When this option is used, floating-point operations in higherprecisions are not available to the programmer without setting the FPUcontrol word explicitly.
Setting the rounding of floating-point operations to less than the default80 bits can speed some programs by 2% or more. Note that some mathematicallibraries assume that extended-precision (80-bit) floating-point operationsare enabled by default; routines in such libraries could suffer significantloss of accuracy, typically through so-called “catastrophic cancellation”,when this option is used to set the precision to less than extended precision.
-mdaz-ftz ¶The flush-to-zero (FTZ) and denormals-are-zero (DAZ) flags in the MXCSR registerare used to control floating-point calculations.SSE and AVX instructionsincluding scalar and vector instructions could benefit from enabling the FTZand DAZ flags when-mdaz-ftz is specified. Don’t set FTZ/DAZ flagswhen-mno-daz-ftz or-shared is specified,-mdaz-ftzwill set FTZ/DAZ flags even with-shared.
-mstackrealign ¶Realign the stack at entry. On the x86, the-mstackrealignoption generates an alternate prologue and epilogue that realigns therun-time stack if necessary. This supports mixing legacy codes that keep4-byte stack alignment with modern codes that keep 16-byte stack alignment forSSE compatibility. See also the attributeforce_align_arg_pointer,applicable to individual functions.
-mpreferred-stack-boundary=num ¶Attempt to keep the stack boundary aligned to a 2 raised tonumbyte boundary. If-mpreferred-stack-boundary is not specified,the default is 4 (16 bytes or 128 bits).
Warning: When generating code for the x86-64 architecture withSSE extensions disabled,-mpreferred-stack-boundary=3 can beused to keep the stack boundary aligned to 8 byte boundary. Sincex86-64 ABI require 16 byte stack alignment, this is ABI incompatible andintended to be used in controlled environment where stack space isimportant limitation. This option leads to wrong code when functionscompiled with 16 byte stack alignment (such as functions from a standardlibrary) are called with misaligned stack. In this case, SSEinstructions may lead to misaligned memory access traps. In addition,variable arguments are handled incorrectly for 16 byte alignedobjects (including x87 long double and __int128), leading to wrongresults. You must build all modules with-mpreferred-stack-boundary=3, including any libraries. Thisincludes the system libraries and startup modules.
-mincoming-stack-boundary=num ¶Assume the incoming stack is aligned to a 2 raised tonum byteboundary. If-mincoming-stack-boundary is not specified,the one specified by-mpreferred-stack-boundary is used.
On Pentium and Pentium Pro,double andlong double valuesshould be aligned to an 8-byte boundary (see-malign-double) orsuffer significant run time performance penalties. On Pentium III, theStreaming SIMD Extension (SSE) data type__m128 may not workproperly if it is not 16-byte aligned.
To ensure proper alignment of this values on the stack, the stack boundarymust be as aligned as that required by any value stored on the stack.Further, every function must be generated such that it keeps the stackaligned. Thus calling a function compiled with a higher preferredstack boundary from a function compiled with a lower preferred stackboundary most likely misaligns the stack. It is recommended thatlibraries that use callbacks always use the default setting.
This extra alignment does consume extra stack space, and generallyincreases code size. Code that is sensitive to stack space usage, suchas embedded systems and operating system kernels, may want to reduce thepreferred alignment to-mpreferred-stack-boundary=2.
-mmmx ¶-msse-msse2-msse3-mssse3-msse4-msse4a-msse4.1-msse4.2-mavx-mavx2-mavx512f-mavx512cd-mavx512vl-mavx512bw-mavx512dq-mavx512ifma-mavx512vbmi-msha-maes-mpclmul-mclflushopt-mclwb-mfsgsbase-mptwrite-mrdrnd-mf16c-mfma-mpconfig-mwbnoinvd-mfma4-mprfchw-mrdpid-mrdseed-msgx-mxop-mlwp-m3dnow-m3dnowa-mpopcnt-mabm-madx-mbmi-mbmi2-mlzcnt-mfxsr-mxsave-mxsaveopt-mxsavec-mxsaves-mrtm-mhle-mtbm-mmwaitx-mclzero-mpku-mavx512vbmi2-mavx512bf16-mavx512fp16-mgfni-mvaes-mwaitpkg-mvpclmulqdq-mavx512bitalg-mmovdiri-mmovdir64b-menqcmd-muintr-mtsxldtrk-mavx512vpopcntdq-mavx512vp2intersect-mavx512vnni-mavxvnni-mcldemote-mserialize-mamx-tile-mamx-int8-mamx-bf16-mhreset-mkl-mwidekl-mavxifma-mavxvnniint8-mavxneconvert-mcmpccxadd-mamx-fp16-mprefetchi-mraoint-mamx-complex-mavxvnniint16-msm3-msha512-msm4-mapxf-musermsr-mavx10.1-mavx10.2-mamx-avx512-mamx-tf32-mamx-fp8-mmovrs-mamx-movrsThese switches enable the use of instructions in the MMX, SSE,AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES,PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,WBNOINVD, FMA4, PREFETCHW, RDPID, RDSEED, SGX, XOP, LWP, 3DNow!,enhanced 3DNow!, POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE, XSAVEOPT,XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2, GFNI, VAES,WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD,AVX512VPOPCNTDQ, AVX512VNNI, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8,AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT,CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512,SM4, APX_F, USER_MSR, AVX10.1, AVX10.2, AMX-AVX512, AMX-TF32, AMX-FP8, MOVRS,AMX-MOVRS or CLDEMOTE extended instruction sets. Each has a corresponding-mno- option to disable use of these instructions.
These extensions are also available as built-in functions: seex86 Built-in Functions, for details of the functions enabled anddisabled by these switches.
Note that-msse4 enables both SSE4.1 and SSE4.2 support,while-mno-sse4 turns off those features; neither form of theoption affects SSE4A support, controlled separately by-msse4a.
To generate SSE/SSE2 instructions automatically from floating-pointcode (as opposed to 387 instructions), see-mfpmath=sse.
GCC depresses SSEx instructions when-mavx is used. Instead, itgenerates new AVX instructions or AVX equivalence for all SSEx instructionswhen needed.
These options enable GCC to use these extended instructions ingenerated code, even without-mfpmath=sse. Applications thatperform run-time CPU detection must compile separate files for eachsupported architecture, using the appropriate flags. In particular,the file containing the CPU detection code should be compiled withoutthese options.
-mdump-tune-features ¶This option instructs GCC to dump the names of the x86 performancetuning features and default settings. The names can be used in-mtune-ctrl=feature-list.
-mtune-ctrl=feature-list ¶This option is used to do fine grain control of x86 code generation features.feature-list is a comma separated list offeature names. See also-mdump-tune-features. When specified, thefeature is turnedon if it is not preceded with ‘^’, otherwise, it is turned off.-mtune-ctrl=feature-list is intended to be used by GCCdevelopers. Using it may lead to code paths not covered by testing and canpotentially result in compiler ICEs or runtime errors.
-mno-default ¶This option instructs GCC to turn off all tunable features. See also-mtune-ctrl=feature-list and-mdump-tune-features.
-mcld ¶This option instructs GCC to emit acld instruction in the prologueof functions that use string instructions. String instructions depend onthe DF flag to select between autoincrement or autodecrement mode. While theABI specifies the DF flag to be cleared on function entry, some operatingsystems violate this specification by not clearing the DF flag in theirexception dispatchers. The exception handler can be invoked with the DF flagset, which leads to wrong direction mode when string instructions are used.This option can be enabled by default on 32-bit x86 targets by configuringGCC with the--enable-cld configure option. Generation ofcldinstructions can be suppressed with the-mno-cld compiler optionin this case.
-mvzeroupper ¶This option instructs GCC to emit avzeroupper instructionbefore a transfer of control flow out of the function to minimizethe AVX to SSE transition penalty as well as remove unnecessaryzeroupperintrinsics.
-mprefer-avx128 ¶This option instructs GCC to use 128-bit AVX instructions instead of256-bit AVX instructions in the auto-vectorizer.
-mprefer-vector-width=opt ¶This option instructs GCC to useopt-bit vector width in instructionsinstead of default on the selected platform.
-mpartial-vector-fp-math ¶This option enables GCC to generate floating-point operations that mightaffect the set of floating-point status flags on partial vectors, wherevector elements reside in the low part of the 128-bit SSE register. Unless-fno-trapping-math is specified, the compiler guarantees correctbehavior by sanitizing all input operands to have zeroes in the unusedupper part of the vector register. Note that by using built-in functionsor inline assembly with partial vector arguments, NaNs, denormal or invalidvalues can leak into the upper part of the vector, causing possibleperformance issues when-fno-trapping-math is in effect. Theseissues can be mitigated by manually sanitizing the upper part of the partialvector argument register or by using-mdaz-ftz to setdenormals-are-zero (DAZ) flag in the MXCSR register.
This option is enabled by default.
-mmove-max=bits ¶This option instructs GCC to set the maximum number of bits can bemoved from memory to memory efficiently tobits. The validbits are 128, 256 and 512.
-mstore-max=bits ¶This option instructs GCC to set the maximum number of bits can bestored to memory efficiently tobits. The validbits are128, 256 and 512.
No extra limitations applied to GCC other than defined by the selected platform.
Prefer 128-bit vector width for instructions.
Prefer 256-bit vector width for instructions.
Prefer 512-bit vector width for instructions.
-mnoreturn-no-callee-saved-registers ¶This option optimizes functions withnoreturn attribute or_Noreturn specifier by not saving in the function prologue callee-savedregisters which are used in the function (except for theBPregister). This option can interfere with debugging of the caller of thenoreturn function or any function further up in the call stack, so itis not enabled by default.
-mcx16 ¶This option enables GCC to generateCMPXCHG16B instructions in 64-bitcode to implement compare-and-exchange operations on 16-byte aligned 128-bitobjects. This is useful for atomic updates of data structures exceeding onemachine word in size. The compiler uses this instruction to implementLegacy__sync Built-in Functions for Atomic Memory Access. However, forBuilt-in Functions for Memory Model Aware Atomic Operations operating on128-bit integers, a library call is always used.
-msahf ¶This option enables generation ofSAHF instructions in 64-bit code.Early Intel Pentium 4 CPUs with Intel 64 support,prior to the introduction of Pentium 4 G1 step in December 2005,lacked theLAHF andSAHF instructionswhich are supported by AMD64.These are load and store instructions, respectively, for certain status flags.In 64-bit mode, theSAHF instruction is used to optimizefmod,drem, andremainder built-in functions;seeOther Built-in Functions Provided by GCC for details.
-mmovbe ¶This option enables use of themovbe instruction to optimizebyte swapping of four and eight byte entities.
-mshstk ¶The-mshstk option enables shadow stack built-in functionsfrom x86 Control-flow Enforcement Technology (CET).
-mcrc32 ¶This option enables built-in functions__builtin_ia32_crc32qi,__builtin_ia32_crc32hi,__builtin_ia32_crc32si and__builtin_ia32_crc32di to generate thecrc32 machine instruction.
-mmwait ¶This option enables built-in functions__builtin_ia32_monitor,and__builtin_ia32_mwait to generate themonitor andmwait machine instructions.
-mrecip ¶This option enables use ofRCPSS andRSQRTSS instructions(and their vectorized variantsRCPPS andRSQRTPS)with an additional Newton-Raphson stepto increase precision instead ofDIVSS andSQRTSS(and their vectorizedvariants) for single-precision floating-point arguments. These instructionsare generated only when-funsafe-math-optimizations is enabledtogether with-ffinite-math-only and-fno-trapping-math.Note that while the throughput of the sequence is higher than the throughputof the non-reciprocal instruction, the precision of the sequence can bedecreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
Note that GCC implements1.0f/sqrtf(x) in terms ofRSQRTSS(orRSQRTPS) already with-ffast-math (or the above optioncombination), and doesn’t need-mrecip.
Also note that GCC emits the above sequence with additional Newton-Raphson stepfor vectorized single-float division and vectorizedsqrtf(x)already with-ffast-math (or the above option combination), anddoesn’t need-mrecip.
-mrecip=opt ¶This option controls which reciprocal estimate instructionsmay be used.opt is a comma-separated list of options, which maybe preceded by a ‘!’ to invert the option:
Enable all estimate instructions.
Enable the default instructions, equivalent to-mrecip.
Disable all estimate instructions, equivalent to-mno-recip.
Enable the approximation for scalar division.
Enable the approximation for vectorized division.
Enable the approximation for scalar square root.
Enable the approximation for vectorized square root.
So, for example,-mrecip=all,!sqrt enablesall of the reciprocal approximations, except for square root.
-mveclibabi=type ¶Specifies the ABI type to use for vectorizing intrinsics using an externallibrary. Supported values fortype are ‘svml’ for the Intel shortvector math library, ‘aocl’ for the math library (LibM) from AMDOptimizing CPU Libraries (AOCL) and ‘acml’ for the end-of-life AMD coremath library (to which AOCL-LibM is the successor).To use this option, both-ftree-vectorize and-funsafe-math-optimizations have to be enabled, and an SVML or ACMLABI-compatible library must be specified at link time.
GCC currently emits calls tovmldExp2,vmldLn2,vmldLog102,vmldPow2,vmldTanh2,vmldTan2,vmldAtan2,vmldAtanh2,vmldCbrt2,vmldSinh2,vmldSin2,vmldAsinh2,vmldAsin2,vmldCosh2,vmldCos2,vmldAcosh2,vmldAcos2,vmlsExp4,vmlsLn4,vmlsLog104,vmlsPow4,vmlsTanh4,vmlsTan4,vmlsAtan4,vmlsAtanh4,vmlsCbrt4,vmlsSinh4,vmlsSin4,vmlsAsinh4,vmlsAsin4,vmlsCosh4,vmlsCos4,vmlsAcosh4 andvmlsAcos4 forcorresponding function type when-mveclibabi=svml is used,amd_vrs4_acosf,amd_vrs16_acosf,amd_vrd8_asin,amd_vrs4_asinf,amd_vrs8_asinf,amd_vrs16_asinf,amd_vrd2_atan,amd_vrd8_atan,amd_vrs4_atanf,amd_vrs8_atanf,amd_vrs16_atanf,amd_vrd2_cos,amd_vrd4_cos,amd_vrd8_cos,amd_vrs4_cosf,amd_vrs8_cosf,amd_vrs16_cosf,amd_vrs4_coshf,amd_vrs8_coshf,amd_vrd2_erf,amd_vrd4_erf,amd_vrd8_erf,amd_vrs4_erff,amd_vrs8_erff,amd_vrs16_erff,amd_vrd2_exp,amd_vrd4_exp,amd_vrd8_exp,amd_vrs4_expf,amd_vrs8_expf,amd_vrs16_expf,amd_vrd2_exp10,amd_vrs4_exp10f,amd_vrd2_exp2,amd_vrd4_exp2,amd_vrd8_exp2,amd_vrs4_exp2f,amd_vrs8_exp2f,amd_vrs16_exp2f,amd_vrs4_expm1f,amd_vrd2_log,amd_vrd4_log,amd_vrd8_log,amd_vrs4_logf,amd_vrs8_logf,amd_vrs16_logf,amd_vrd2_log10,amd_vrs4_log10f,amd_vrs8_log10f,amd_vrs16_log10f,amd_vrd2_log1p,amd_vrs4_log1pf,amd_vrd2_log2,amd_vrd4_log2,amd_vrd8_log2,amd_vrs4_log2f,amd_vrs8_log2f,amd_vrs16_log2f,amd_vrd2_pow,amd_vrd4_pow,amd_vrd8_pow,amd_vrs4_powf,amd_vrs8_powf,amd_vrs16_powf,amd_vrd2_sin,amd_vrd4_sin,amd_vrd8_sin,amd_vrs4_sinf,amd_vrs8_sinf,amd_vrs16_sinf,amd_vrd2_tan,amd_vrd4_tan,amd_vrd8_tan,amd_vrs16_tanf,amd_vrs4_tanhf,amd_vrs8_tanhf,amd_vrs16_tanhf for the corresponding functiontype when-mveclibabi=aocl is used, and__vrd2_sin,__vrd2_cos,__vrd2_exp,__vrd2_log,__vrd2_log2,__vrd2_log10,__vrs4_sinf,__vrs4_cosf,__vrs4_expf,__vrs4_logf,__vrs4_log2f,__vrs4_log10f and__vrs4_powf for the corresponding function typewhen-mveclibabi=acml is used.
-mabi=name ¶Generate code for the specified calling convention. Permissible valuesare ‘sysv’ for the ABI used on GNU/Linux and other systems, and‘ms’ for the Microsoft ABI. The default is to use the MicrosoftABI when targeting Microsoft Windows and the SysV ABI on all other systems.You can control this behavior for specific functions byusing the function attributesms_abi andsysv_abi.SeeDeclaring Attributes of Functions.
-mforce-indirect-call ¶Force all calls to functions to be indirect. This is usefulwhen using Intel Processor Trace where it generates more precise timinginformation for function calls.
-mmanual-endbr ¶Insert ENDBR instruction at function entry only via thecf_checkfunction attribute. This is useful when used with the option-fcf-protection=branch to control ENDBR insertion at thefunction entry.
-mcet-switch ¶By default, CET instrumentation is turned off on switch statements thatuse a jump table and indirect branch track is disabled. Since jumptables are stored in read-only memory, this does not result in a directloss of hardening. But if the jump table index is attacker-controlled,the indirect jump may not be constrained by CET. This option turns onCET instrumentation to enable indirect branch track for switch statementswith jump tables which leads to the jump targets reachable via any indirectjumps.
-mcall-ms2sysv-xlogues ¶Due to differences in 64-bit ABIs, any Microsoft ABI function that calls aSystem V ABI function must consider RSI, RDI and XMM6-15 as clobbered. Bydefault, the code for saving and restoring these registers is emitted inline,resulting in fairly lengthy prologues and epilogues. Using-mcall-ms2sysv-xlogues emits prologues and epilogues thatuse stubs in the static portion of libgcc to perform these saves and restores,thus reducing function size at the cost of a few extra instructions.
-mtls-dialect=type ¶Generate code to access thread-local storage using the ‘gnu’ or‘gnu2’ conventions. ‘gnu’ is the conservative default;‘gnu2’ is more efficient, but it may add compile- and run-timerequirements that cannot be satisfied on all systems.
-mpush-args ¶-mno-push-argsUse PUSH operations to store outgoing parameters. This method is shorterand usually equally fast as method using SUB/MOV operations and is enabledby default. In some cases disabling it may improve performance because ofimproved scheduling and reduced dependencies.
-maccumulate-outgoing-args ¶If enabled, the maximum amount of space required for outgoing arguments iscomputed in the function prologue. This is faster on most modern CPUsbecause of reduced dependencies, improved scheduling and reduced stack usagewhen the preferred stack boundary is not equal to 2. The drawback is a notableincrease in code size. This switch implies-mno-push-args.
-mthreads ¶Support thread-safe exception handling on MinGW. Programs that relyon thread-safe exception handling must compile and link all code with the-mthreads option. When compiling,-mthreads defines-D_MT; when linking, it links in a special thread helper library-lmingwthrd which cleans up per-thread exception-handling data.
-mms-bitfields ¶-mno-ms-bitfieldsEnable/disable bit-field layout compatible with the native MicrosoftWindows compiler.
Ifpacked is used on a structure, or if bit-fields are used,it may be that the Microsoft ABI lays out the structure differentlythan the way GCC normally does. Particularly when moving packeddata between functions compiled with GCC and the native Microsoft compiler(either via function call or as data in a file), it may be necessary to accesseither format.
This option is enabled by default for Microsoft Windowstargets. This behavior can also be controlled locally by use of variableor type attributes. For more information, seex86 Variable Attributesandx86 Type Attributes.
The Microsoft structure layout algorithm is fairly simple with the exceptionof the bit-field packing.The padding and alignment of members of structures and whether a bit-fieldcan straddle a storage-unit boundary are determine by these rules:
aligned attribute or thepack pragma),whichever is less. For structures, unions, and arrays,the alignment requirement is the largest alignment requirement of its members.Every object is allocated an offset so that:offset % alignment_requirement == 0
MSVC interprets zero-length bit-fields in the following ways:
For example:
struct { unsigned long bf_1 : 12; unsigned long : 0; unsigned long bf_2 : 12; } t1;The size oft1 is 8 bytes with the zero-length bit-field. If thezero-length bit-field were removed,t1’s size would be 4 bytes.
foo, and thealignment of the zero-length bit-field is greater than the member that follows it,bar,bar is aligned as the type of the zero-length bit-field.For example:
struct { char foo : 4; short : 0; char bar; } t2;struct { char foo : 4; short : 0; double bar; } t3;Fort2,bar is placed at offset 2, rather than offset 1.Accordingly, the size oft2 is 4. Fort3, the zero-lengthbit-field does not affect the alignment ofbar or, as a result, the sizeof the structure.
Taking this into account, it is important to note the following:
t2 has a size of 4 bytes, since the zero-length bit-field follows anormal bit-field, and is of type short.struct { char foo : 6; long : 0; } t4;Here,t4 takes up 4 bytes.
struct { char foo; long : 0; char bar; } t5;Here,t5 takes up 2 bytes.
-mno-align-stringops ¶Do not align the destination of inlined string operations. This switch reducescode size and improves performance in case the destination is already aligned,but GCC doesn’t know about it.
-minline-all-stringops ¶By default GCC inlines string operations only when the destination isknown to be aligned to least a 4-byte boundary.This enables more inlining and increases codesize, but may improve performance of code that depends on fastmemcpy andmemset for short lengths.The option enables inline expansion ofstrlen for allpointer alignments.
-minline-stringops-dynamically ¶For string operations of unknown size, use run-time checks withinline code for small blocks and a library call for large blocks.
-mstringop-strategy=alg ¶Override the internal decision heuristic for the particular algorithm to usefor inlining string operations. The allowed values foralg are:
Expand using i386rep prefix of the specified size.
Expand into an inline loop.
Always use a library call.
-mmemcpy-strategy=strategy ¶Override the internal decision heuristic to decide if__builtin_memcpyshould be inlined and what inline algorithm to use when the expected sizeof the copy operation is known.strategyis a comma-separated list ofalg:max_size:dest_align triplets.alg is specified in-mstringop-strategy,max_size specifiesthe max byte size with which inline algorithmalg is allowed. For the lasttriplet, themax_size must be-1. Themax_size of the tripletsin the list must be specified in increasing order. The minimal byte size foralg is0 for the first triplet andmax_size + 1 of thepreceding range.
-mmemset-strategy=strategy ¶The option is similar to-mmemcpy-strategy= except that it is to control__builtin_memset expansion.
-momit-leaf-frame-pointer ¶Don’t keep the frame pointer in a register for leaf functions. Thisavoids the instructions to save, set up, and restore frame pointers andmakes an extra register available in leaf functions. The option-momit-leaf-frame-pointer removes the frame pointer for leaf functions,which might make debugging harder.
-mtls-direct-seg-refs ¶-mno-tls-direct-seg-refsControls whether TLS variables may be accessed with offsets from theTLS segment register (%gs for 32-bit,%fs for 64-bit),or whether the thread base pointer must be added. Whether or not thisis valid depends on the operating system, and whether it maps thesegment to cover the entire TLS area.
For systems that use the GNU C Library, the default is on.
-msse2avx ¶-mno-sse2avxSpecify that the assembler should encode SSE instructions with VEXprefix. The option-mavx turns this on by default.
-mfentry ¶-mno-fentryIf profiling is active (-pg), put the profilingcounter call before the prologue.Note: On x86 architectures the attributems_hook_prologueisn’t possible at the moment for-mfentry and-pg.
-mrecord-mcount ¶-mno-record-mcountIf profiling is active (-pg), generate a __mcount_loc sectionthat contains pointers to each profiling call. This is useful forautomatically patching and out calls.
-mnop-mcount ¶-mno-nop-mcountIf profiling is active (-pg), generate the calls tothe profiling functions as NOPs. This is useful when theyshould be patched in later dynamically. This is likely onlyuseful together with-mrecord-mcount.
-minstrument-return=type ¶Instrument function exit in -pg -mfentry instrumented functions withcall to specified function. This only instruments true returns endingwith ret, but not sibling calls ending with jump. Valid typesarenone to not instrument,call to generate a call to __return__,ornop5 to generate a 5 byte nop.
-mrecord-return ¶-mno-record-returnGenerate a __return_loc section pointing to all return instrumentation code.
-mfentry-name=name ¶Set name of __fentry__ symbol called at function entry for -pg -mfentry functions.
-mfentry-section=name ¶Set name of section to record -mrecord-mcount calls (default __mcount_loc).
-mskip-rax-setup ¶-mno-skip-rax-setupWhen generating code for the x86-64 architecture with SSE extensionsdisabled,-mskip-rax-setup can be used to skip setting up RAXregister when there are no variable arguments passed in vector registers.
Warning: Since RAX register is used to avoid unnecessarilysaving vector registers on stack when passing variable arguments, theimpacts of this option are callees may waste some stack space,misbehave or jump to a random location. GCC 4.4 or newer don’t havethose issues, regardless the RAX register value.
-m8bit-idiv ¶-mno-8bit-idivOn some processors, like Intel Atom, 8-bit unsigned integer divide ismuch faster than 32-bit/64-bit integer divide. This option generates arun-time check. If both dividend and divisor are within range of 0to 255, 8-bit unsigned integer divide is used instead of32-bit/64-bit integer divide.
-mavx256-split-unaligned-load ¶-mavx256-split-unaligned-storeSplit 32-byte AVX unaligned load and store.
-mstack-protector-guard=guard ¶-mstack-protector-guard-reg=reg-mstack-protector-guard-offset=offset-mstack-protector-guard-symbol=symbolGenerate stack protection code using canary atguard. Supportedlocations are ‘global’ for global canary or ‘tls’ for per-threadcanary in the TLS block (the default). This option has effect only when-fstack-protector or-fstack-protector-all is specified.
With the latter choice the options-mstack-protector-guard-reg=reg and-mstack-protector-guard-offset=offset furthermore specifywhich segment register (%fs or%gs) to use as base registerfor reading the canary, and from what offset from that base register.The default for those is as specified in the relevant ABI.
-mstack-protector-guard-symbol=symbol overridesthe offset with a symbol reference to a canary in the TLS block.
-mgeneral-regs-only ¶Generate code that uses only the general-purpose registers. Thisprevents the compiler from using floating-point, vector, mask and boundregisters.
-mrelax-cmpxchg-loop ¶When emitting a compare-and-swap loop forLegacy__sync Built-in Functions for Atomic Memory AccessandBuilt-in Functions for Memory Model Aware Atomic Operations lacking a native instruction, optimizefor the highly contended case by issuing an atomic load before theCMPXCHG instruction, and using thePAUSE instructionto save CPU power when restarting the loop.
-mindirect-branch=choice ¶Convert indirect call and jump withchoice. The default is‘keep’, which keeps indirect call and jump unmodified.‘thunk’ converts indirect call and jump to call and return thunk.‘thunk-inline’ converts indirect call and jump to inlined calland return thunk. ‘thunk-extern’ converts indirect call and jumpto external call and return thunk provided in a separate object file.You can control this behavior for a specific function by using thefunction attributeindirect_branch. SeeDeclaring Attributes of Functions.
Note that-mcmodel=large is incompatible with-mindirect-branch=thunk and-mindirect-branch=thunk-extern since the thunk function maynot be reachable in the large code model.
Note that-mindirect-branch=thunk-extern is compatible with-fcf-protection=branch since the external thunk can be madeto enable control-flow check.
-mfunction-return=choice ¶Convert function return withchoice. The default is ‘keep’,which keeps function return unmodified. ‘thunk’ converts functionreturn to call and return thunk. ‘thunk-inline’ converts functionreturn to inlined call and return thunk. ‘thunk-extern’ convertsfunction return to external call and return thunk provided in a separateobject file. You can control this behavior for a specific function byusing the function attributefunction_return.SeeDeclaring Attributes of Functions.
Note that-mindirect-return=thunk-extern is compatible with-fcf-protection=branch since the external thunk can be madeto enable control-flow check.
Note that-mcmodel=large is incompatible with-mfunction-return=thunk and-mfunction-return=thunk-extern since the thunk function maynot be reachable in the large code model.
-mindirect-branch-register ¶Force indirect call and jump via register.
-mharden-sls=choice ¶Generate code to mitigate against straight line speculation (SLS) withchoice. The default is ‘none’ which disables all SLShardening. ‘return’ enables SLS hardening for function returns.‘indirect-jmp’ enables SLS hardening for indirect jumps.‘all’ enables all SLS hardening.
-mindirect-branch-cs-prefix ¶Add CS prefix to call and jmp to indirect thunk with branch target inr8-r15 registers so that the call and jmp instruction length is 6 bytesto allow them to be replaced with ‘lfence; call *%r8-r15’ or‘lfence; jmp *%r8-r15’ at run-time.
-mapx-inline-asm-use-gpr32 ¶For inline asm support with APX, by default the EGPR feature wasdisabled to prevent potential illegal instruction with EGPR occurs.To invoke egpr usage in inline asm, use new compiler option-mapx-inline-asm-use-gpr32 and user should ensure the instructionsupports EGPR.
These ‘-m’ switches are supported in addition to the aboveon x86-64 processors in 64-bit environments.
-m32 ¶-m64-mx32-m16-miamcuGenerate code for a 16-bit, 32-bit or 64-bit environment.The-m32 option setsint,long, and pointer typesto 32 bits, andgenerates code that runs in 32-bit mode.
The-m64 option setsint to 32 bits andlong and pointertypes to 64 bits, and generates code for the x86-64 architecture.For Darwin only the-m64 option also turns off the-fno-picand-mdynamic-no-pic options.
The-mx32 option setsint,long, and pointer typesto 32 bits, andgenerates code for the x86-64 architecture.
The-m16 option is the same as-m32, except for thatit outputs the.code16gcc assembly directive at the beginning ofthe assembly output so that the binary can run in 16-bit mode.
The-miamcu option generates code which conforms to Intel MCUpsABI. It requires the-m32 option to be turned on.
-mno-red-zone ¶Do not use a so-called “red zone” for x86-64 code. The red zone is mandatedby the x86-64 ABI; it is a 128-byte area beyond the location of thestack pointer that is not modified by signal or interrupt handlersand therefore can be used for temporary data without adjusting the stackpointer. The flag-mno-red-zone disables this red zone.
-mcmodel=small ¶Generate code for the small code model: the program and its symbols mustbe linked in the lower 2 GB of the address space. Pointers are 64 bits.Programs can be statically or dynamically linked. This is the defaultcode model.
-mcmodel=kernel ¶Generate code for the kernel code model. The kernel runs in thenegative 2 GB of the address space.This model has to be used for Linux kernel code.
-mcmodel=medium ¶Generate code for the medium model: the program is linked in the lower 2GB of the address space. Small symbols are also placed there. Symbolswith sizes larger than-mlarge-data-threshold are put intolarge data or BSS sections and can be located above 2GB. Programs canbe statically or dynamically linked.
-mcmodel=large ¶Generate code for the large model. This model makes no assumptionsabout addresses and sizes of sections.
-maddress-mode=long ¶Generate code for long address mode. This is only supported for 64-bitand x32 environments. It is the default address mode for 64-bitenvironments.
-maddress-mode=short ¶Generate code for short address mode. This is only supported for 32-bitand x32 environments. It is the default address mode for 32-bit andx32 environments.
-mneeded ¶-mno-neededEmit GNU_PROPERTY_X86_ISA_1_NEEDED GNU property for Linux target toindicate the micro-architecture ISA level required to execute the binary.
-mno-direct-extern-access ¶Without-fpic nor-fPIC, always use the GOT pointerto access external symbols. With-fpic or-fPIC,treat access to protected symbols as local symbols. The default is-mdirect-extern-access.
Warning: shared libraries compiled with-mno-direct-extern-access and executable compiled with-mdirect-extern-access may not be binary compatible ifprotected symbols are used in shared libraries and executable.
-munroll-only-small-loops ¶Controls conservative small loop unrolling. It is default enabled byO2, and unrolls loop with less than 4 insns by 1 time. Explicit-f[no-]unroll-[all-]loops would disable this flag to avoid anyunintended unrolling behavior that user does not want.
-mlam=choice ¶LAM(linear-address masking) allows special bits in the pointer to be usedfor metadata. The default is ‘none’. With ‘u48’, pointer bits inpositions 62:48 can be used for metadata; With ‘u57’, pointer bits inpositions 62:57 can be used for metadata.
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