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These ‘-m’ options are supported on the SPARC:
-mno-app-regs ¶-mapp-regsSpecify-mapp-regs to generate output using the global registers2 through 4, which the SPARC SVR4 ABI reserves for applications. Like theglobal register 1, each global register 2 through 4 is then treated as anallocable register that is clobbered by function calls. This is the default.
To be fully SVR4 ABI-compliant at the cost of some performance loss,specify-mno-app-regs. You should compile libraries and systemsoftware with this option.
-mflat ¶-mno-flatWith-mflat, the compiler does not generate save/restore instructionsand uses a “flat” or single register window model. This model is compatiblewith the regular register window model. The local registers and the inputregisters (0–5) are still treated as “call-saved” registers and aresaved on the stack as needed.
With-mno-flat (the default), the compiler generates save/restoreinstructions (except for leaf functions). This is the normal operating mode.
-mfpu ¶-mhard-floatGenerate output containing floating-point instructions. This is thedefault.
-mno-fpu ¶-msoft-floatGenerate output containing library calls for floating point.Warning: the requisite libraries are not available for all SPARCtargets. Normally the facilities of the machine’s usual C compiler areused, but this cannot be done directly in cross-compilation. You must makeyour own arrangements to provide suitable library functions forcross-compilation. The embedded targets ‘sparc-*-aout’ and‘sparclite-*-*’ do provide software floating-point support.
-msoft-float changes the calling convention in the output file;therefore, it is only useful if you compileall of a program withthis option. In particular, you need to compilelibgcc.a, thelibrary that comes with GCC, with-msoft-float in order forthis to work.
-mhard-quad-float ¶Generate output containing quad-word (long double) floating-pointinstructions.
-msoft-quad-float ¶Generate output containing library calls for quad-word (long double)floating-point instructions. The functions called are those specifiedin the SPARC ABI. This is the default.
As of this writing, there are no SPARC implementations that have hardwaresupport for the quad-word floating-point instructions. They all invokea trap handler for one of these instructions, and then the trap handleremulates the effect of the instruction. Because of the trap handler overhead,this is much slower than calling the ABI library routines. Thus the-msoft-quad-float option is the default.
-mno-unaligned-doubles ¶-munaligned-doublesAssume that doubles have 8-byte alignment. This is the default.
With-munaligned-doubles, GCC assumes that doubles have 8-bytealignment only if they are contained in another type, or if they have anabsolute address. Otherwise, it assumes they have 4-byte alignment.Specifying this option avoids some rare compatibility problems with codegenerated by other compilers. It is not the default because it resultsin a performance loss, especially for floating-point code.
-muser-mode ¶-mno-user-modeDo not generate code that can only run in supervisor mode. This is relevantonly for thecasa instruction emitted for the LEON3 processor. Thisis the default.
-mfaster-structs ¶-mno-faster-structsWith-mfaster-structs, the compiler assumes that structuresshould have 8-byte alignment. This enables the use of pairs ofldd andstd instructions for copies in structureassignment, in place of twice as manyld andst pairs.However, the use of this changed alignment directly violates the SPARCABI. Thus, it’s intended only for use on targets where the developeracknowledges that their resulting code is not directly in line withthe rules of the ABI.
-mstd-struct-return ¶-mno-std-struct-returnWith-mstd-struct-return, the compiler generates checking codein functions returning structures or unions to detect size mismatchesbetween the two sides of function calls, as per the 32-bit ABI.
The default is-mno-std-struct-return. This option has no effectin 64-bit mode.
-mcpu=cpu_type ¶Set the instruction set, register set, and instruction scheduling parametersfor machine typecpu_type. Supported values forcpu_type are‘v7’, ‘cypress’, ‘v8’, ‘supersparc’, ‘hypersparc’,‘leon’, ‘leon3’, ‘leon3v7’, ‘leon5’, ‘sparclite’,‘f930’, ‘f934’, ‘sparclite86x’, ‘sparclet’, ‘tsc701’,‘v9’, ‘ultrasparc’, ‘ultrasparc3’, ‘niagara’,‘niagara2’, ‘niagara3’, ‘niagara4’, ‘niagara7’ and‘m8’.
Native Solaris and GNU/Linux toolchains also support the value ‘native’,which selects the best architecture option for the host processor.-mcpu=native has no effect if GCC does not recognizethe processor.
Default instruction scheduling parameters are used for values that selectan architecture and not an implementation. These are ‘v7’, ‘v8’,‘sparclite’, ‘sparclet’, ‘v9’.
Here is a list of each supported architecture and their supportedimplementations.
cypress, leon3v7
supersparc, hypersparc, leon, leon3, leon5
f930, f934, sparclite86x
tsc701
ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4,niagara7, m8
By default (unless configured otherwise), GCC generates code for the V7variant of the SPARC architecture. With-mcpu=cypress, the compileradditionally optimizes it for the Cypress CY7C602 chip, as used in theSPARCStation/SPARCServer 3xx series. This is also appropriate for the olderSPARCStation 1, 2, IPX etc.
With-mcpu=v8, GCC generates code for the V8 variant of the SPARCarchitecture. The only difference from V7 code is that the compiler emitsthe integer multiply and integer divide instructions which exist in SPARC-V8but not in SPARC-V7. With-mcpu=supersparc, the compiler additionallyoptimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and2000 series.
With-mcpu=sparclite, GCC generates code for the SPARClite variant ofthe SPARC architecture. This adds the integer multiply, integer divide stepand scan (ffs) instructions which exist in SPARClite but not in SPARC-V7.With-mcpu=f930, the compiler additionally optimizes it for theFujitsu MB86930 chip, which is the original SPARClite, with no FPU. With-mcpu=f934, the compiler additionally optimizes it for the FujitsuMB86934 chip, which is the more recent SPARClite with FPU.
With-mcpu=sparclet, GCC generates code for the SPARClet variant ofthe SPARC architecture. This adds the integer multiply, multiply/accumulate,integer divide step and scan (ffs) instructions which exist in SPARCletbut not in SPARC-V7. With-mcpu=tsc701, the compiler additionallyoptimizes it for the TEMIC SPARClet chip.
With-mcpu=v9, GCC generates code for the V9 variant of the SPARCarchitecture. This adds 64-bit integer and floating-point move instructions,3 additional floating-point condition code registers and conditional moveinstructions. With-mcpu=ultrasparc, the compiler additionallyoptimizes it for the Sun UltraSPARC I/II/IIi chips. With-mcpu=ultrasparc3, the compiler additionally optimizes it for theSun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With-mcpu=niagara, the compiler additionally optimizes it forSun UltraSPARC T1 chips. With-mcpu=niagara2, the compileradditionally optimizes it for Sun UltraSPARC T2 chips. With-mcpu=niagara3, the compiler additionally optimizes it for SunUltraSPARC T3 chips. With-mcpu=niagara4, the compileradditionally optimizes it for Sun UltraSPARC T4 chips. With-mcpu=niagara7, the compiler additionally optimizes it forOracle SPARC M7 chips. With-mcpu=m8, the compileradditionally optimizes it for Oracle M8 chips.
-mtune=cpu_type ¶Set the instruction scheduling parameters for machine typecpu_type, but do not set the instruction set or register set that theoption-mcpu=cpu_type does.
The same values for-mcpu=cpu_type can be used for-mtune=cpu_type, but the only useful values are thosethat select a particular CPU implementation. Those are‘cypress’, ‘supersparc’, ‘hypersparc’, ‘leon’,‘leon3’, ‘leon3v7’, ‘leon5’, ‘f930’, ‘f934’,‘sparclite86x’, ‘tsc701’, ‘ultrasparc’,‘ultrasparc3’, ‘niagara’, ‘niagara2’, ‘niagara3’,‘niagara4’, ‘niagara7’ and ‘m8’. With native Solarisand GNU/Linux toolchains, ‘native’ can also be used.
-mv8plus ¶-mno-v8plusWith-mv8plus, GCC generates code for the SPARC-V8+ ABI. Thedifference from the V8 ABI is that the global and out registers areconsidered 64 bits wide. This is enabled by default on Solaris in 32-bitmode for all SPARC-V9 processors.
-mvis ¶-mno-visWith-mvis, GCC generates code that takes advantage of the UltraSPARCVisual Instruction Set extensions. The default is-mno-vis.
-mvis2 ¶-mno-vis2With-mvis2, GCC generates code that takes advantage ofversion 2.0 of the UltraSPARC Visual Instruction Set extensions. Thedefault is-mvis2 when targeting a cpu that supports suchinstructions, such as UltraSPARC-III and later. Setting-mvis2also sets-mvis.
-mvis3 ¶-mno-vis3With-mvis3, GCC generates code that takes advantage ofversion 3.0 of the UltraSPARC Visual Instruction Set extensions. Thedefault is-mvis3 when targeting a cpu that supports suchinstructions, such as niagara-3 and later. Setting-mvis3also sets-mvis2 and-mvis.
-mvis3b ¶-mno-vis3bWith-mvis3b, GCC generates code that takes advantage ofversion 3.0 of the UltraSPARC Visual Instruction Set extensions, plusthe additional VIS instructions introduced in the Oracle SPARCArchitecture 2011. The default is-mvis3b when targetinga cpu that supports such instructions, such as niagara-7 and later.Setting-mvis3b also sets-mvis3,-mvis2and-mvis.
-mvis4 ¶-mno-vis4With-mvis4, GCC generates code that takes advantage ofversion 4.0 of the UltraSPARC Visual Instruction Set extensions. Thedefault is-mvis4 when targeting a cpu that supports suchinstructions, such as niagara-7 and later. Setting-mvis4also sets-mvis3b,-mvis3,-mvis2 and-mvis.
-mvis4b ¶-mno-vis4bWith-mvis4b, GCC generates code that takes advantage ofversion 4.0 of the UltraSPARC Visual Instruction Set extensions, plusthe additional VIS instructions introduced in the Oracle SPARCArchitecture 2017. The default is-mvis4b when targeting acpu that supports such instructions, such as m8 and later. Setting-mvis4b also sets-mvis4,-mvis3b,-mvis3,-mvis2 and-mvis.
-mcbcond ¶-mno-cbcondWith-mcbcond, GCC generates code that takes advantage of the UltraSPARCCompare-and-Branch-on-Condition instructions. The default is-mcbcondwhen targeting a CPU that supports such instructions, such as Niagara-4 andlater.
-mfmaf ¶-mno-fmafWith-mfmaf, GCC generates code that takes advantage of the UltraSPARCFused Multiply-Add Floating-point instructions. The default is-mfmafwhen targeting a CPU that supports such instructions, such as Niagara-3 andlater.
-mfsmuld ¶-mno-fsmuldWith-mfsmuld, GCC generates code that takes advantage of theFloating-point Multiply Single to Double (FsMULd) instruction. The default is-mfsmuld when targeting a CPU supporting the architecture versions V8or V9 with FPU except-mcpu=leon.
-mpopc ¶-mno-popcWith-mpopc, GCC generates code that takes advantage of the UltraSPARCPopulation Count instruction. The default is-mpopcwhen targeting a CPU that supports such an instruction, such as Niagara-2 andlater.
-msubxc ¶-mno-subxcWith-msubxc, GCC generates code that takes advantage of the UltraSPARCSubtract-Extended-with-Carry instruction. The default is-msubxcwhen targeting a CPU that supports such an instruction, such as Niagara-7 andlater.
-mfix-at697f ¶Enable the documented workaround for the single erratum of the Atmel AT697Fprocessor (which corresponds to erratum #13 of the AT697E processor).
-mfix-ut699 ¶Enable the documented workarounds for the floating-point errata and the datacache nullify errata of the UT699 processor.
-mfix-ut700 ¶Enable the documented workaround for the back-to-back store errata ofthe UT699E/UT700 processor.
-mfix-gr712rc ¶Enable the documented workaround for the back-to-back store errata ofthe GR712RC processor.
These ‘-m’ options are supported in addition to the aboveon SPARC-V9 processors in 64-bit environments:
-m32 ¶-m64Generate code for a 32-bit or 64-bit environment.The 32-bit environment sets int, long and pointer to 32 bits.The 64-bit environment sets int to 32 bits and long and pointerto 64 bits.
-mptr32 ¶-mptr64Use 32- or 64-bit pointers, respectively. Unlike the-m32 and-m64 options, this affects only the pointer size and not the ABI.
-mcmodel=which ¶Set the code model to one of
The Medium/Low code model: 64-bit addresses, programsmust be linked in the low 32 bits of memory. Programs can be staticallyor dynamically linked.
The Medium/Middle code model: 64-bit addresses, programsmust be linked in the low 44 bits of memory, the text and data segments mustbe less than 2GB in size and the data segment must be located within 2GB ofthe text segment.
The Medium/Anywhere code model: 64-bit addresses, programsmay be linked anywhere in memory, the text and data segments must be lessthan 2GB in size and the data segment must be located within 2GB of thetext segment.
The Medium/Anywhere code model for embedded systems:64-bit addresses, the text and data segments must be less than 2GB insize, both starting anywhere in memory (determined at link time). Theglobal register %g4 points to the base of the data segment. Programsare statically linked and PIC is not supported.
-mmemory-model=mem-model ¶Set the memory model in force on the processor to one of
The default memory model for the processor and operating system.
Relaxed Memory Order
Partial Store Order
Total Store Order
Sequential Consistency
These memory models are formally defined in Appendix D of the SPARC-V9architecture manual, as set in the processor’sPSTATE.MM field.
-mstack-bias ¶-mno-stack-biasWith-mstack-bias, GCC assumes that the stack pointer, andframe pointer if present, are offset by −2047 which must be added backwhen making stack frame references. This is the default in 64-bit mode.Otherwise, assume no such offset is present.
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