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These ‘-m’ options are defined for the SH implementations:
-m1 ¶Generate code for the SH1.
-m2 ¶Generate code for the SH2.
-m2e ¶Generate code for the SH2e.
-m2a-nofpu ¶Generate code for the SH2a without FPU, or for a SH2a-FPU in such a waythat the floating-point unit is not used.
-m2a-single-only ¶Generate code for the SH2a-FPU, in such a way that no double-precisionfloating-point operations are used.
-m2a-single ¶Generate code for the SH2a-FPU assuming the floating-point unit is insingle-precision mode by default.
-m2a ¶Generate code for the SH2a-FPU assuming the floating-point unit is indouble-precision mode by default.
-m3 ¶Generate code for the SH3.
-m3e ¶Generate code for the SH3e.
-m4-nofpu ¶Generate code for the SH4 without a floating-point unit.
-m4-single-only ¶Generate code for the SH4 with a floating-point unit that onlysupports single-precision arithmetic.
-m4-single ¶Generate code for the SH4 assuming the floating-point unit is insingle-precision mode by default.
-m4 ¶Generate code for the SH4.
-m4-100 ¶Generate code for SH4-100.
-m4-100-nofpu ¶Generate code for SH4-100 in such a way that thefloating-point unit is not used.
-m4-100-single ¶Generate code for SH4-100 assuming the floating-point unit is insingle-precision mode by default.
-m4-100-single-only ¶Generate code for SH4-100 in such a way that no double-precisionfloating-point operations are used.
-m4-200 ¶Generate code for SH4-200.
-m4-200-nofpu ¶Generate code for SH4-200 without in such a way that thefloating-point unit is not used.
-m4-200-single ¶Generate code for SH4-200 assuming the floating-point unit is insingle-precision mode by default.
-m4-200-single-only ¶Generate code for SH4-200 in such a way that no double-precisionfloating-point operations are used.
-m4-300 ¶Generate code for SH4-300.
-m4-300-nofpu ¶Generate code for SH4-300 without in such a way that thefloating-point unit is not used.
-m4-300-single ¶Generate code for SH4-300 in such a way that no double-precisionfloating-point operations are used.
-m4-300-single-only ¶Generate code for SH4-300 in such a way that no double-precisionfloating-point operations are used.
-m4-340 ¶Generate code for SH4-340 (no MMU, no FPU).
-m4-400 ¶Generate code for SH4-400 (no MMU, no FPU).
-m4-500 ¶Generate code for SH4-500 (no FPU). Passes-isa=sh4-nofpu to theassembler.
-m4a-nofpu ¶Generate code for the SH4al-dsp, or for a SH4a in such a way that thefloating-point unit is not used.
-m4a-single-only ¶Generate code for the SH4a, in such a way that no double-precisionfloating-point operations are used.
-m4a-single ¶Generate code for the SH4a assuming the floating-point unit is insingle-precision mode by default.
-m4a ¶Generate code for the SH4a.
-m4al ¶Same as-m4a-nofpu, except that it implicitly passes-dsp to the assembler. GCC doesn’t generate any DSPinstructions at the moment.
-mb ¶Compile code for the processor in big-endian mode.
-ml ¶Compile code for the processor in little-endian mode.
-mdalign ¶Align doubles at 64-bit boundaries. Note that this changes the callingconventions, and thus some functions from the standard C library donot work unless you recompile it first with-mdalign.
-mrelax ¶Shorten some address references at link time, when possible; uses thelinker option-relax.
-mbigtable ¶Use 32-bit offsets inswitch tables. The default is to use16-bit offsets.
-mbitops ¶Enable the use of bit manipulation instructions on SH2A.
-mfmovd ¶Enable the use of the instructionfmovd. Check-mdalign foralignment constraints.
-mrenesas ¶-mno-renesasComply with the calling conventions defined by Renesas. The default for alltargets of the SH toolchain is-mno-renesas, which uses thecalling conventions defined for GCC before the Renesas conventions wereavailable.
-mnomacsave ¶Mark theMAC register as call-clobbered, even if-mrenesas is given.
-mieee ¶-mno-ieeeControl the IEEE compliance of floating-point comparisons, which affects thehandling of cases where the result of a comparison is unordered. By default-mieee is implicitly enabled. If-ffinite-math-only isenabled-mno-ieee is implicitly set, which results in fasterfloating-point greater-equal and less-equal comparisons. The implicit settingscan be overridden by specifying either-mieee or-mno-ieee.
-minline-ic_invalidate ¶-mno-inline-ic_invalidateInline code to invalidate instruction cache entries after setting upnested function trampolines.This option has no effect if-musermode is in effect and theselected code generation option (e.g.-m4) does not allowthe use of theicbi instruction.If the selected code generation option does not allow the use of theicbiinstruction, and-musermode is not in effect, the inlined codemanipulates the instruction cache address array directly with an associativewrite. This not only requires privileged mode at run time, but it alsofails if the cache line had been mapped via the TLB and has become unmapped.
-misize ¶Dump instruction size and location in the assembly code.
-matomic-model=model ¶Sets the model of atomic operations and additional parameters as acomma-separated list. For details on the atomic built-in functions seeBuilt-in Functions for Memory Model Aware Atomic Operations. The following models and parameters are supported:
Disable compiler generated atomic sequences and emit library calls for atomicoperations. This is the default if the target is notsh*-*-linux*.
Generate GNU/Linux-compatible gUSA software atomic sequences for the atomicbuilt-in functions. The generated atomic sequences require additional supportfrom the interrupt/exception handling code of the system and are only suitablefor SH3* and SH4* single-core systems. This option is enabled by default whenthe target issh*-*-linux* and SH3* or SH4*. When the target is SH4A,this option also partially utilizes the hardware atomic instructionsmovli.l andmovco.l to create more efficient code, unless‘strict’ is specified.
Generate software atomic sequences that use a variable in the thread controlblock. This is a variation of the gUSA sequences which can also be used onSH1* and SH2* targets. The generated atomic sequences require additionalsupport from the interrupt/exception handling code of the system and are onlysuitable for single-core systems. When using this model,the ‘gbr-offset=’ parameter has to be specified as well.
Generate software atomic sequences that temporarily disable interrupts bysettingSR.IMASK = 1111. This model works only when the program runsin privileged mode and is only suitable for single-core systems. Additionalsupport from the interrupt/exception handling code of the system is notrequired. This model is enabled by default when the target issh*-*-linux* and SH1* or SH2*.
Generate hardware atomic sequences using themovli.l andmovco.linstructions only. This is only available on SH4A and is suitable formulti-core systems.Since the hardware instructions support only 32-bit atomicvariables, access to 8- or 16-bit variables is emulated with 32-bit accesses.Code compiled with this option is also compatible with other softwareatomic model interrupt/exception handling systems if executed on an SH4Asystem. Additional support from the interrupt/exception handling code of thesystem is not required for this model.
This parameter specifies the offset in bytes of the variable in the threadcontrol block structure that should be used by the generated atomic sequenceswhen the ‘soft-tcb’ model has been selected. For other models thisparameter is ignored. The specified value must be an integer multiple of fourand in the range 0-1020.
This parameter prevents mixed usage of multiple atomic models, even if theyare compatible, and makes the compiler generate atomic sequences of thespecified model only.
-mtas ¶Generate thetas.b opcode for__atomic_test_and_set.Notice that depending on the particular hardware and software configurationthis can degrade overall performance due to the operand cache line flushesthat are implied by thetas.b instruction. On multi-core SH4Aprocessors thetas.b instruction must be used with caution since itcan result in data corruption for certain cache configurations.
-mprefergot ¶When generating position-independent code, emit function calls usingthe Global Offset Table instead of the Procedure Linkage Table.
-musermode ¶-mno-usermodeDon’t allow (allow) the compiler to generate privileged mode code. Specifying-musermode also implies-mno-inline-ic_invalidate if theinlined code would not work in user mode.-musermode is the defaultwhen the target issh*-*-linux*. If the target is SH1* or SH2*-musermode has no effect, since there is no user mode.
-multcost=number ¶Set the cost to assume for a multiply instruction.
-mdiv=strategy ¶Set the division strategy to be used for integer division operations.strategy can be one of:
Calls a library function that uses the single-step division instructiondiv1 to perform the operation. Division by zero calculates anunspecified result and does not trap. This is the default except for SH4,SH2A and SHcompact.
Calls a library function that performs the operation in double precisionfloating point. Division by zero causes a floating-point exception. This isthe default for SHcompact with FPU. Specifying this for targets that do nothave a double-precision FPU defaults tocall-div1.
Calls a library function that uses a lookup table for small divisors andthediv1 instruction with case distinction for larger divisors.Division by zero calculates an unspecified result and does not trap.This is the defaultfor SH4. Specifying this for targets that do not have dynamic shiftinstructions defaults tocall-div1.
When a division strategy has not been specified, the default strategy isselected based on the current target. For SH2A the default strategy is touse thedivs anddivu instructions instead of library functioncalls.
-maccumulate-outgoing-args ¶-mno-accumulate-outgoing-argsReserve space once for outgoing arguments in the function prologue ratherthan around each call. This is generally beneficial for performance andsize, and also needed for unwinding to avoid changing the stack framearound conditional code.-maccumulate-outgoing-args isenabled the default.
-mdivsi3_libfunc=name ¶Set the name of the library function used for 32-bit signed division toname.This only affects the name used in the ‘call’ division strategies,and the compiler still expects the same sets of input/output/clobberedregisters as if this option were not present.
-mfixed-range=register-range ¶Generate code treating the given register range as fixed registers.A fixed register is one that the register allocator cannot use. This isuseful when compiling kernel code. A register range is specified astwo registers separated by a dash. Multiple register ranges can bespecified separated by a comma.
-mbranch-cost=num ¶Assumenum to be the cost for a branch instruction. Higher numbersmake the compiler try to generate more branch-free code if possible.If not specified the value is selected depending on the processor type thatis being compiled for.
-mzdcbranch ¶-mno-zdcbranchAssume (do not assume) that zero displacement conditional branch instructionsbt andbf are fast. If-mzdcbranch is specified, thecompiler prefers zero displacement branch code sequences. This isenabled by default when generating code for SH4 and SH4A.It can be explicitly disabled by specifying-mno-zdcbranch.
-mcbranch-force-delay-slot ¶Force the usage of delay slots for conditional branches, which stuffs thedelay slot with anop if a suitable instruction cannot be found.By defaultthis option is disabled. It can be enabled to work around hardware bugs asfound in the original SH7055.
-mfsca ¶-mno-fscaAllow or disallow the compiler to emit thefsca instruction for sineand cosine approximations. The option-mfsca must be used incombination with-funsafe-math-optimizations.It is enabled by default when generating code for SH4A.Using-mno-fsca disables sine and cosineapproximations even if-funsafe-math-optimizations is in effect.
-mfsrra ¶-mno-fsrraAllow or disallow the compiler to emit thefsrra instruction forreciprocal square root approximations. The option-mfsrramust be used in combination with-funsafe-math-optimizations and-ffinite-math-only.It is enabled by default when generating code for SH4A.Using-mno-fsrra disables reciprocal square root approximationseven if-funsafe-math-optimizations and-ffinite-math-onlyare in effect.
-mpretend-cmove ¶-mno-pretend-cmovePrefer or don’t prefer zero-displacement conditional branches forconditional move instruction patterns.This can result in faster code on the SH4 processor.
-mfdpic ¶-mno-fdpicGenerate code using the FDPIC ABI.
-mlra ¶-mno-lraUse the new LRA register allocator. By default, the old “reload”allocator is used.
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