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These ‘-m’ options are defined for the IBM RS/6000 and PowerPC:
-mcpu=cpu_type ¶Set architecture type, register usage, andinstruction scheduling parameters for machine typecpu_type.Supported values forcpu_type are ‘401’, ‘403’,‘405’, ‘405fp’, ‘440’, ‘440fp’, ‘464’, ‘464fp’,‘476’, ‘476fp’, ‘505’, ‘601’, ‘602’, ‘603’,‘603e’, ‘604’, ‘604e’, ‘620’, ‘630’, ‘740’,‘7400’, ‘7450’, ‘750’, ‘801’, ‘821’, ‘823’,‘860’, ‘970’, ‘8540’, ‘a2’, ‘e300c2’,‘e300c3’, ‘e500mc’, ‘e500mc64’, ‘e5500’,‘e6500’, ‘ec603e’, ‘G3’, ‘G4’, ‘G5’,‘titan’, ‘power3’, ‘power4’, ‘power5’, ‘power5+’,‘power6’, ‘power6x’, ‘power7’, ‘power8’,‘power9’, ‘power10’, ‘power11’, ‘powerpc’, ‘powerpc64’,‘powerpc64le’, ‘rs64’, and ‘native’.
-mcpu=powerpc,-mcpu=powerpc64, and-mcpu=powerpc64le specify pure 32-bit PowerPC (eitherendian), 64-bit big endian PowerPC and 64-bit little endian PowerPCarchitecture machine types, with an appropriate, generic processormodel assumed for scheduling purposes.
Specifying ‘native’ as cpu type detects and selects thearchitecture option that corresponds to the host processor of thesystem performing the compilation.-mcpu=native has no effect if GCC does not recognize theprocessor.
The other options specify a specific processor. Code generated underthose options runs best on that processor, and may not run at all onothers.
The-mcpu options automatically enable or disable thefollowing options:
-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple-mpopcntb -mpopcntd -mpowerpc64-mpowerpc-gpopt -mpowerpc-gfxopt-mmulhw -mdlmzb -mmfpgpr -mvsx-mcrypto -mhtm -mpower8-fusion-mquad-memory -mquad-memory-atomic -mfloat128-mfloat128-hardware -mprefixed -mpcrel -mmma-mrop-protect
The particular options set for any particular CPU varies betweencompiler versions, depending on what setting seems to produce optimalcode for that CPU; it doesn’t necessarily reflect the actual hardware’scapabilities. If you wish to set an individual option to a particularvalue, you may specify it after the-mcpu option, like-mcpu=970 -mno-altivec.
On AIX, the-maltivec and-mpowerpc64 options arenot enabled or disabled by the-mcpu option at present becauseAIX does not have full support for these options. You may stillenable or disable them individually if you’re sure it’ll work in yourenvironment.
In other cases, we recommend you use the-mcpu=cpu_type optionrather than the options that control generation of specific instructions.
-mtune=cpu_type ¶Set the instruction scheduling parameters for machine typecpu_type, but do not set the architecture type or register usage,as-mcpu=cpu_type does. The samevalues forcpu_type are used for-mtune as for-mcpu. If both are specified, the code generated uses thearchitecture and registers set by-mcpu, but thescheduling parameters set by-mtune.
-mpowerpc64 ¶-mno-powerpc64The-mpowerpc64 option allows GCC to generate the additional64-bit instructions that are found in the full PowerPC64 architectureand to treat GPRs as 64-bit, doubleword quantities. GCC defaults to-mno-powerpc64.
-mcmodel=small ¶Generate PowerPC64 code for the small model: The TOC is limited to64k.
-mcmodel=medium ¶Generate PowerPC64 code for the medium model: The TOC and other staticdata may be up to a total of 4G in size. This is the default for 64-bitLinux.
-mcmodel=large ¶Generate PowerPC64 code for the large model: The TOC may be up to 4Gin size. Other data and code is only limited by the 64-bit addressspace.
-mprofile-kernel ¶This option is available on PowerPC64 GNU/Linux targets. When used with-pg, it causes calls tomcount to be inserted before thefunction prologue instead of after it.
-maltivec ¶-mno-altivecGenerate code that uses (does not use) AltiVec instructions, and alsoenable the use of built-in functions that allow more direct access tothe AltiVec instruction set. You may also need to set-mabi=altivec to adjust the current ABI with AltiVec ABIenhancements.
When-maltivec is used, the element order for AltiVec intrinsicssuch asvec_splat,vec_extract, andvec_insertmatch array element order corresponding to the endianness of thetarget. That is, element zero identifies the leftmost element in avector register when targeting a big-endian platform, and identifiesthe rightmost element in a vector register when targeting alittle-endian platform.
-mpowerpc-gpopt ¶-mno-powerpc-gpoptSpecifying-mpowerpc-gpopt allowsGCC to use the optional PowerPC architecture instructions in theGeneral Purpose group, including floating-point square root. Specifying
-mpowerpc-gfxopt ¶-mno-powerpc-gfxopt-mpowerpc-gfxopt allows GCC touse the optional PowerPC architecture instructions in the Graphicsgroup, including floating-point select.
-mmfcrf ¶-mno-mfcrfThe-mmfcrf option allows GCC to generate the move fromcondition register field instruction implemented on the POWER4processor and other processors that support the PowerPC V2.01architecture.
-mpopcntb ¶-mno-popcntbThe-mpopcntb option allows GCC to generate the popcount anddouble-precision FP reciprocal estimate instruction implemented on thePOWER5 processor and other processors that support the PowerPC V2.02architecture.
-mpopcntd ¶-mno-popcntdThe-mpopcntd option allows GCC to generate the popcountinstruction implemented on the POWER7 processor and other processorsthat support the PowerPC V2.06 architecture.
-mfprnd ¶-mno-fprndThe-mfprnd option allows GCC to generate the FP round tointeger instructions implemented on the POWER5+ processor and otherprocessors that support the PowerPC V2.03 architecture.
-mcmpb ¶-mno-cmpbThe-mcmpb option allows GCC to generate the compare bytesinstruction implemented on the POWER6 processor and other processorsthat support the PowerPC V2.05 architecture.
-mhard-dfp ¶-mno-hard-dfpThe-mhard-dfp option allows GCC to generate the decimalfloating-point instructions implemented on some POWER processors.
-mvrsave ¶-mno-vrsaveGenerate VRSAVE instructions when generating AltiVec code.
-msecure-plt ¶Generate code that allowsld andld.soto build executables and sharedlibraries with non-executable.plt and.got sections.This is a PowerPC32-bit SYSV ABI option.
-mbss-plt ¶Generate code that uses a BSS.plt section thatld.sofills in, andrequires.plt and.gotsections that are both writable and executable.This is a PowerPC 32-bit SYSV ABI option.
-msplit-patch-nops ¶When adding NOPs for a patchable area via the-fpatchable-function-entry option emit the “before” NOPs in frontof the global entry point and the “after” NOPs after the local entry point.This makes the sequence of NOPs not consecutive when a global entry pointis generated. Without this option the NOPs are emitted directly before andafter the local entry point, making them consecutive but moving global andlocal entry point further apart. If only a single entry point is generatedthis option has no effect.
-misel ¶-mno-iselThis switch enables or disables the generation of ISEL instructions.
-mvsx ¶-mno-vsxGenerate code that uses (does not use) vector/scalar (VSX)instructions, and also enable the use of built-in functions that allowmore direct access to the VSX instruction set.
-mcrypto ¶-mno-cryptoEnable the use (disable) of the built-in functions that allow directaccess to the cryptographic instructions that were added in version2.07 of the PowerPC ISA.
-mhtm ¶-mno-htmEnable (disable) the use of the built-in functions that allow directaccess to the Hardware Transactional Memory (HTM) instructions thatwere added in version 2.07 of the PowerPC ISA.
-mpower8-fusion ¶-mno-power8-fusionGenerate code that keeps (does not keeps) some integer operationsadjacent so that the instructions can be fused together on power8 andlater processors.
-mquad-memory ¶-mno-quad-memoryGenerate code that uses (does not use) the non-atomic quad word memoryinstructions. The-mquad-memory option requires use of64-bit mode.
-mquad-memory-atomic ¶-mno-quad-memory-atomicGenerate code that uses (does not use) the atomic quad word memoryinstructions. The-mquad-memory-atomic option requires use of64-bit mode.
-mfloat128 ¶-mno-float128Enable/disable the__float128 keyword for IEEE 128-bit floating pointand use either software emulation for IEEE 128-bit floating point orhardware instructions.
The VSX instruction set (-mvsx) must be enabled to use the IEEE128-bit floating point support. The IEEE 128-bit floating point is onlysupported on Linux.
The default for-mfloat128 is enabled on PowerPC Linuxsystems using the VSX instruction set, and disabled on other systems.
If you use the ISA 3.0 instruction set (-mcpu=power9) on a64-bit system, the IEEE 128-bit floating point support also enablesthe generation of ISA 3.0 IEEE 128-bit floating point instructions.Otherwise, if you do not specify generation of ISA 3.0 instructions or youare targeting a 32-bit big-endian system, IEEE 128-bit floating pointis handled with software emulation.
-mfloat128-hardware ¶-mno-float128-hardwareEnable/disable using ISA 3.0 hardware instructions to support the__float128 data type.
The default for-mfloat128-hardware is enabled on PowerPCLinux systems using the ISA 3.0 instruction set, and disabled on othersystems.
-m32 ¶-m64Generate code for 32-bit or 64-bit environments of Darwin and SVR4targets (including GNU/Linux). The 32-bit environment sets int, longand pointer to 32 bits and generates code that runs on any PowerPCvariant. The 64-bit environment sets int to 32 bits and long andpointer to 64 bits, and generates code for PowerPC64, as for-mpowerpc64.
-mfull-toc ¶-mno-fp-in-toc-mno-sum-in-toc-mminimal-tocModify generation of the TOC (Table Of Contents), which is created forevery executable file. The-mfull-toc option is selected bydefault. In that case, GCC allocates at least one TOC entry foreach unique non-automatic variable reference in your program. GCCalso places floating-point constants in the TOC. However, only16,384 entries are available in the TOC.
If you receive a linker error message that saying you have overflowedthe available TOC space, you can reduce the amount of TOC space usedwith the-mno-fp-in-toc and-mno-sum-in-toc options.-mno-fp-in-toc prevents GCC from putting floating-pointconstants in the TOC and-mno-sum-in-toc forces GCC togenerate code to calculate the sum of an address and a constant atrun time instead of putting that sum into the TOC. You may specify oneor both of these options. Each causes GCC to produce very slightlyslower and larger code at the expense of conserving TOC space.
If you still run out of space in the TOC even when you specify both ofthese options, specify-mminimal-toc instead. This option causesGCC to make only one TOC entry for every file. When you specify thisoption, GCC produces code that is slower and larger but whichuses extremely little TOC space. You may wish to use this optiononly on files that contain less frequently-executed code.
-maix64 ¶-maix32Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bitlong type, and the infrastructure needed to support them.Specifying-maix64 implies-mpowerpc64,while-maix32 disables the 64-bit ABI andimplies-mno-powerpc64. GCC defaults to-maix32.
-mxl-compat ¶-mno-xl-compatProduce code that conforms more closely to IBM XL compiler semanticswhen using AIX-compatible ABI. Pass floating-point arguments toprototyped functions beyond the register save area (RSA) on the stackin addition to argument FPRs. Do not assume that most significantdouble in 128-bit long double value is properly rounded when comparingvalues and converting to double. Use XL symbol names for long doublesupport routines.
The AIX calling convention was extended but not initially documented tohandle an obscure K&R C case of calling a function that takes theaddress of its arguments with fewer arguments than declared. IBM XLcompilers access floating-point arguments that do not fit in theRSA from the stack when a subroutine is compiled withoutoptimization. Because always storing floating-point arguments on thestack is inefficient and rarely needed, this option is not enabled bydefault and only is necessary when calling subroutines compiled by IBMXL compilers without optimization.
-mpe ¶SupportIBM RS/6000 SPParallel Environment (PE). Link anapplication written to use message passing with special startup code toenable the application to run. The system must have PE installed in thestandard location (/usr/lpp/ppe.poe/), or thespecs filemust be overridden with the-specs= option to specify theappropriate directory location. The Parallel Environment does notsupport threads, so the-mpe option and the-pthreadoption are incompatible.
-malign-natural ¶-malign-powerOn AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option-malign-natural overrides the ABI-defined alignment of largertypes, such as floating-point doubles, on their natural size-based boundary.The option-malign-power instructs GCC to follow the ABI-specifiedalignment rules. GCC defaults to the standard alignment defined in the ABI.
On 64-bit Darwin, natural alignment is the default, and-malign-poweris not supported.
-msoft-float ¶-mhard-floatGenerate code that does not use (uses) the floating-point register set.Software floating-point emulation is provided if you use the-msoft-float option, and pass the option to GCC when linking.
-mmultiple ¶-mno-multipleGenerate code that uses (does not use) the load multiple wordinstructions and the store multiple word instructions. Theseinstructions are generated by default on POWER systems, and notgenerated on PowerPC systems. Do not use-mmultiple on little-endianPowerPC systems, since those instructions do not work when theprocessor is in little-endian mode. The exceptions are PPC740 andPPC750 which permit these instructions in little-endian mode.
-mupdate ¶-mno-updateGenerate code that uses (does not use) the load or store instructionsthat update the base register to the address of the calculated memorylocation. These instructions are generated by default. If you use-mno-update, there is a small window between the time that thestack pointer is updated and the address of the previous frame isstored, which means code that walks the stack frame across interrupts orsignals may get corrupted data.
-mavoid-indexed-addresses ¶-mno-avoid-indexed-addressesGenerate code that tries to avoid (not avoid) the use of indexed loador store instructions. These instructions can incur a performancepenalty on Power6 processors in certain situations, such as whenstepping through large arrays that cross a 16M boundary. This optionis enabled by default when targeting Power6 and disabled otherwise.
-mfused-madd ¶-mno-fused-maddGenerate code that uses (does not use) the floating-point multiply andaccumulate instructions. These instructions are generated by defaultif hardware floating point is used. The machine-dependent-mfused-madd option is now mapped to the machine-independent-ffp-contract=fast option, and-mno-fused-madd ismapped to-ffp-contract=off.
-mmulhw ¶-mno-mulhwGenerate code that uses (does not use) the half-word multiply andmultiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.These instructions are generated by default when targeting thoseprocessors.
-mdlmzb ¶-mno-dlmzbGenerate code that uses (does not use) the string-search ‘dlmzb’instruction on the IBM 405, 440, 464 and 476 processors. This instruction isgenerated by default when targeting those processors.
-mno-bit-align ¶-mbit-alignOn System V.4 and embedded PowerPC systems do not (do) force structuresand unions that contain bit-fields to be aligned to the base type of thebit-field.
For example, by default a structure containing nothing but 8unsigned bit-fields of length 1 is aligned to a 4-byteboundary and has a size of 4 bytes. By using-mno-bit-align,the structure is aligned to a 1-byte boundary and is 1 byte insize.
-mbit-word ¶-mno-bit-wordAllow bit-fields to cross word boundaries.
-mno-strict-align ¶-mstrict-alignOn System V.4 and embedded PowerPC systems do not (do) assume thatunaligned memory references are handled by the system.
-mrelocatable ¶-mno-relocatableGenerate code that allows (does not allow) a static executable to berelocated to a different address at run time. A simple embeddedPowerPC system loader should relocate the entire contents of.got2 and 4-byte locations listed in the.fixup section,a table of 32-bit addresses generated by this option. For this towork, all objects linked together must be compiled with-mrelocatable or-mrelocatable-lib.-mrelocatable code aligns the stack to an 8-byte boundary.
-mrelocatable-lib ¶-mno-relocatable-libLike-mrelocatable,-mrelocatable-lib generates a.fixup section to allow static executables to be relocated atrun time, but-mrelocatable-lib does not use the smaller stackalignment of-mrelocatable. Objects compiled with-mrelocatable-lib may be linked with objects compiled withany combination of the-mrelocatable options.
-mlittle ¶-mlittle-endianOn System V.4 and embedded PowerPC systems compile code for theprocessor in little-endian mode. The-mlittle-endian option isthe same as-mlittle.
-mbig ¶-mbig-endianOn System V.4 and embedded PowerPC systems compile code for theprocessor in big-endian mode. The-mbig-endian option isthe same as-mbig.
-mdynamic-no-pic ¶On Darwin / macOS systems, compile code so that it is notrelocatable, but that its external references are relocatable. Theresulting code is suitable for applications, but not sharedlibraries.
-msingle-pic-base ¶Treat the register used for PIC addressing as read-only, rather thanloading it in the prologue for each function. The runtime system isresponsible for initializing this register with an appropriate valuebefore execution begins.
-mprioritize-restricted-insns=priority ¶This option controls the priority that is assigned todispatch-slot restricted instructions during the second schedulingpass. The argumentpriority takes the value ‘0’, ‘1’,or ‘2’ to assign no, highest, or second-highest (respectively)priority to dispatch-slot restrictedinstructions.
-msched-costly-dep=dependence_type ¶This option controls which dependences are considered costlyby the target during instruction scheduling. The argumentdependence_type takes one of the following values:
No dependence is costly.
All dependences are costly.
A true dependence from store to load is costly.
Any dependence from store to load is costly.
Any dependence for which the latency is greater than or equal tonumber is costly.
-minsert-sched-nops=scheme ¶This option controls which NOP insertion scheme is used duringthe second scheduling pass. The argumentscheme takes one of thefollowing values:
Don’t insert NOPs.
Pad with NOPs any dispatch group that has vacant issue slots,according to the scheduler’s grouping.
Insert NOPs to force costly dependent insns intoseparate groups. Insert exactly as many NOPs as needed to force an insnto a new group, according to the estimated processor grouping.
Insert NOPs to force costly dependent insns intoseparate groups. Insertnumber NOPs to force an insn to a new group.
-mcall-sysv ¶On System V.4 and embedded PowerPC systems compile code using callingconventions that adhere to the March 1995 draft of the System VApplication Binary Interface, PowerPC processor supplement. This is thedefault unless you configured GCC using ‘powerpc-*-eabiaix’.
-mcall-sysv-eabi ¶-mcall-eabiSpecify both-mcall-sysv and-meabi options.
-mcall-sysv-noeabi ¶Specify both-mcall-sysv and-mno-eabi options.
-mcall-aixdesc ¶On System V.4 and embedded PowerPC systems compile code for the AIXoperating system.
-mcall-linux ¶On System V.4 and embedded PowerPC systems compile code for theLinux-based GNU system.
-mcall-freebsd ¶On System V.4 and embedded PowerPC systems compile code for theFreeBSD operating system.
-mcall-netbsd ¶On System V.4 and embedded PowerPC systems compile code for theNetBSD operating system.
-mcall-openbsd ¶On System V.4 and embedded PowerPC systems compile code for theOpenBSD operating system.
-mtraceback=traceback_type ¶Select the type of traceback table. Valid values fortraceback_typeare ‘full’, ‘part’, and ‘no’.
-maix-struct-return ¶Return all structures in memory (as specified by the AIX ABI).
-msvr4-struct-return ¶Return structures smaller than 8 bytes in registers (as specified by theSVR4 ABI).
-mabi=abi-type ¶Extend the current ABI with a particular extension, or remove such extension.Valid values are: ‘altivec’, ‘no-altivec’,‘ibmlongdouble’, ‘ieeelongdouble’,‘elfv1’, ‘elfv2’,and for AIX: ‘vec-extabi’, ‘vec-default’.
-mabi=ibmlongdouble ¶Change the current ABI to use IBM extended-precision long double.This is not likely to work if your system defaults to using IEEEextended-precision long double. If you change the long double typefrom IEEE extended-precision, the compiler issues a warning unlessyou use the-Wno-psabi option (seeOptions to Request or Suppress Warnings).Requires-mlong-double-128 to be enabled.
-mabi=ieeelongdouble ¶Change the current ABI to use IEEE extended-precision long double.This is not likely to work if your system defaults to using IBMextended-precision long double. If you change the long double typefrom IBM extended-precision, the compiler issues a warning unlessyou use the-Wno-psabi option (seeOptions to Request or Suppress Warnings).Requires-mlong-double-128 to be enabled.
-mabi=elfv1 ¶Change the current ABI to use the ELFv1 ABI.This is the default ABI for big-endian PowerPC 64-bit Linux.Overriding the default ABI requires special system support and islikely to fail in spectacular ways.
-mabi=elfv2 ¶Change the current ABI to use the ELFv2 ABI.This is the default ABI for little-endian PowerPC 64-bit Linux.Overriding the default ABI requires special system support and islikely to fail in spectacular ways.
-mgnu-attribute ¶-mno-gnu-attributeEmit .gnu_attribute assembly directives to set tag/value pairs in a.gnu.attributes section that specify ABI variations in functionparameters or return values.
-mprototype ¶-mno-prototypeOn System V.4 and embedded PowerPC systems assume that all calls tovariable argument functions are properly prototyped. Otherwise, thecompiler must insert an instruction before every non-prototyped call toset or clear bit 6 of the condition code register (CR) toindicate whether floating-point values are passed in the floating-pointregisters in case the function takes variable arguments. With-mprototype, only calls to prototyped variable argument functionsset or clear the bit.
-msim ¶On embedded PowerPC systems, assume that the startup module is calledsim-crt0.o and that the standard C libraries arelibsim.a andlibc.a. This is the default for ‘powerpc-*-eabisim’configurations.
-mmvme ¶On embedded PowerPC systems, assume that the startup module is calledcrt0.o and the standard C libraries arelibmvme.a andlibc.a.
-mads ¶On embedded PowerPC systems, assume that the startup module is calledcrt0.o and the standard C libraries arelibads.a andlibc.a.
-myellowknife ¶On embedded PowerPC systems, assume that the startup module is calledcrt0.o and the standard C libraries arelibyk.a andlibc.a.
-mvxworks ¶On System V.4 and embedded PowerPC systems, specify that you arecompiling for a VxWorks system.
-memb ¶On embedded PowerPC systems, set thePPC_EMB bit in the ELF flagsheader to indicate that ‘eabi’ extended relocations are used.
-meabi ¶-mno-eabiOn System V.4 and embedded PowerPC systems do (do not) adhere to theEmbedded Applications Binary Interface (EABI), which is a set ofmodifications to the System V.4 specifications. Selecting-meabimeans that the stack is aligned to an 8-byte boundary, a function__eabi is called frommain to set up the EABIenvironment, and the-msdata option can use bothr2 andr13 to point to two separate small data areas. Selecting-mno-eabi means that the stack is aligned to a 16-byte boundary,no EABI initialization function is called frommain, and the-msdata option only usesr13 to point to a singlesmall data area. The-meabi option is on by default if youconfigured GCC using one of the ‘powerpc*-*-eabi*’ options.
-msdata=eabi ¶On System V.4 and embedded PowerPC systems, put small initializedconst global and static data in the.sdata2 section, whichis pointed to by registerr2. Put small initializednon-const global and static data in the.sdata section,which is pointed to by registerr13. Put small uninitializedglobal and static data in the.sbss section, which is adjacent tothe.sdata section. The-msdata=eabi option isincompatible with the-mrelocatable option. The-msdata=eabi option also sets the-memb option.
-msdata=sysv ¶On System V.4 and embedded PowerPC systems, put small global and staticdata in the.sdata section, which is pointed to by registerr13. Put small uninitialized global and static data in the.sbss section, which is adjacent to the.sdata section.The-msdata=sysv option is incompatible with the-mrelocatable option.
-msdata=default ¶-msdataOn System V.4 and embedded PowerPC systems, if-meabi is used,compile code the same as-msdata=eabi, otherwise compile code thesame as-msdata=sysv.
-msdata=data ¶On System V.4 and embedded PowerPC systems, put small globaldata in the.sdata section. Put small uninitialized globaldata in the.sbss section. Do not use registerr13to address small data however. This is the default behavior unlessother-msdata options are used.
-msdata=none ¶-mno-sdataOn embedded PowerPC systems, put all initialized global and static datain the.data section, and all uninitialized data in the.bss section.
-mreadonly-in-sdata ¶Put read-only objects in the.sdata section as well. This is thedefault.
-mblock-move-inline-limit=num ¶Inline all block moves (such as calls tomemcpy or structurecopies) less than or equal tonum bytes. The minimum value fornum is 32 bytes on 32-bit targets and 64 bytes on 64-bittargets. The default value is target-specific.
-mblock-compare-inline-limit=num ¶Generate non-looping inline code for all block compares (such as callstomemcmp or structure compares) less than or equal tonumbytes. Ifnum is 0, all inline expansion (non-loop and loop) ofblock compare is disabled. The default value is target-specific.
-mblock-compare-inline-loop-limit=num ¶Generate an inline expansion using loop code for all block compares thatare less than or equal tonum bytes, but greater than the limitfor non-loop inline block compare expansion. If the block length is notconstant, at mostnum bytes are compared beforememcmpis called to compare the remainder of the block. The default value istarget-specific.
-mstring-compare-inline-limit=num ¶Compare at mostnum string bytes with inline code.If the difference or end of string is not found at theend of the inline compare, a call tostrcmp orstrncmptakes care of the rest of the comparison. The default is 64 bytes.
-Gnum ¶On embedded PowerPC systems, put global and static items less than orequal tonum bytes into the small data or BSS sections instead ofthe normal data or BSS section. By default,num is 8. The-Gnum switch is also passed to the linker.All modules should be compiled with the same-Gnum value.
-mregnames ¶-mno-regnamesOn System V.4 and embedded PowerPC systems do (do not) emit registernames in the assembly language output using symbolic forms.
-mlongcall ¶-mno-longcallBy default assume that all calls are far away so that a longer and moreexpensive calling sequence is required. This is required for callsfarther than 32 megabytes (33,554,432 bytes) from the current location.A short call is generated if the compiler knowsthe call cannot be that far away. This setting can be overridden bytheshortcall function attribute, or by#pragmalongcall(0).
Some linkers are capable of detecting out-of-range calls and generatingglue code on the fly. On these systems, long calls are unnecessary andgenerate slower code. As of this writing, the AIX linker can do this,as can the GNU linker for PowerPC/64. It is planned to add this featureto the GNU linker for 32-bit PowerPC systems as well.
On PowerPC64 ELFv2 and 32-bit PowerPC systems with newer GNU linkers,GCC can generate long calls using an inline PLT call sequence (see-mpltseq). PowerPC with-mbss-plt and PowerPC64ELFv1 (big-endian) do not support inline PLT calls.
On Darwin/PPC systems,#pragma longcall generatesjbsrcallee, L42, plus abranch island (glue code). The two targetaddresses represent the callee and the branch island. TheDarwin/PPC linker prefers the first address and generates ablcallee if the PPCbl instruction reaches the callee directly;otherwise, the linker generatesbl L42 to call the branchisland. The branch island is appended to the body of thecalling function; it computes the full 32-bit address of the calleeand jumps to it.
On Mach-O (Darwin) systems, this option directs the compiler emit tothe glue for every direct call, and the Darwin linker decides whetherto use or discard it.
In the future, GCC may ignore all longcall specificationswhen the linker is known to generate glue.
-mpltseq ¶-mno-pltseqImplement (do not implement) -fno-plt and long calls using an inlinePLT call sequence that supports lazy linking and long calls tofunctions in dlopen’d shared libraries. Inline PLT calls are onlysupported on PowerPC64 ELFv2 and 32-bit PowerPC systems with newer GNUlinkers, and are enabled by default if the support is detected whenconfiguring GCC, and, in the case of 32-bit PowerPC, if GCC isconfigured with--enable-secureplt.-mpltseq codeand-mbss-plt 32-bit PowerPC relocatable objects may not belinked together.
-mtls-markers ¶-mno-tls-markersMark (do not mark) calls to__tls_get_addr with a relocationspecifying the function argument. The relocation allows the linker toreliably associate function call with argument setup instructions forTLS optimization, which in turn allows GCC to better schedule thesequence.
-mrecip ¶-mno-recipThis option enables use of the reciprocal estimate andreciprocal square root estimate instructions with additionalNewton-Raphson steps to increase precision instead of doing a divide orsquare root and divide for floating-point arguments. You should usethe-ffast-math option when using-mrecip (or atleast-funsafe-math-optimizations,-ffinite-math-only,-freciprocal-math and-fno-trapping-math). Note that while the throughput of thesequence is generally higher than the throughput of the non-reciprocalinstruction, the precision of the sequence can be decreased by up to 2ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal squareroots.
-mrecip=opt ¶This option controls which reciprocal estimate instructionsmay be used.opt is a comma-separated list of options, which maybe preceded by a! to invert the option:
Enable all estimate instructions.
Enable the default instructions, equivalent to-mrecip.
Disable all estimate instructions, equivalent to-mno-recip.
Enable the reciprocal approximation instructions for bothsingle and double precision.
Enable the single-precision reciprocal approximation instructions.
Enable the double-precision reciprocal approximation instructions.
Enable the reciprocal square root approximation instructions for bothsingle and double precision.
Enable the single-precision reciprocal square root approximation instructions.
Enable the double-precision reciprocal square root approximation instructions.
So, for example,-mrecip=all,!rsqrtd enablesall of the reciprocal estimate instructions, except for theFRSQRTE,XSRSQRTEDP, andXVRSQRTEDP instructionswhich handle the double-precision reciprocal square root calculations.
-mrecip-precision ¶-mno-recip-precisionAssume (do not assume) that the reciprocal estimate instructionsprovide higher-precision estimates than is mandated by the PowerPCABI. Selecting-mcpu=power6,-mcpu=power7 or-mcpu=power8 automatically selects-mrecip-precision.The double-precision square root estimate instructions are not generated bydefault on low-precision machines, since they do not provide anestimate that converges after three steps.
-mveclibabi=type ¶Specifies the ABI type to use for vectorizing intrinsics using anexternal library. The only type supported at present is ‘mass’,which specifies to use IBM’s Mathematical Acceleration Subsystem(MASS) libraries for vectorizing intrinsics using external libraries.GCC currently emits calls toacosd2,acosf4,acoshd2,acoshf4,asind2,asinf4,asinhd2,asinhf4,atan2d2,atan2f4,atand2,atanf4,atanhd2,atanhf4,cbrtd2,cbrtf4,cosd2,cosf4,coshd2,coshf4,erfcd2,erfcf4,erfd2,erff4,exp2d2,exp2f4,expd2,expf4,expm1d2,expm1f4,hypotd2,hypotf4,lgammad2,lgammaf4,log10d2,log10f4,log1pd2,log1pf4,log2d2,log2f4,logd2,logf4,powd2,powf4,sind2,sinf4,sinhd2,sinhf4,sqrtd2,sqrtf4,tand2,tanf4,tanhd2, andtanhf4 when generating codefor power7. Both-ftree-vectorize and-funsafe-math-optimizations must also be enabled. The MASSlibraries must be specified at link time.
-mfriz ¶-mno-frizGenerate (do not generate) thefriz instruction when the-funsafe-math-optimizations option is used to optimizerounding of floating-point values to 64-bit integer and back to floatingpoint. Thefriz instruction does not return the same value ifthe floating-point number is too large to fit in an integer.
-mpointers-to-nested-functions ¶-mno-pointers-to-nested-functionsGenerate (do not generate) code to load up the static chain register(r11) when calling through a pointer on AIX and 64-bit Linuxsystems where a function pointer points to a 3-word descriptor givingthe function address, TOC value to be loaded in registerr2, andstatic chain value to be loaded in registerr11. The-mpointers-to-nested-functions is on by default. You cannotcall through pointers to nested functions or pointersto functions compiled in other languages that use the static chain ifyou use-mno-pointers-to-nested-functions.
-msave-toc-indirect ¶-mno-save-toc-indirectGenerate (do not generate) code to save the TOC value in the reservedstack location in the function prologue if the function calls througha pointer on AIX and 64-bit Linux systems. If the TOC value is notsaved in the prologue, it is saved just before the call through thepointer. The-mno-save-toc-indirect option is the default.
-mcompat-align-parm ¶-mno-compat-align-parmGenerate (do not generate) code to pass structure parameters with amaximum alignment of 64 bits, for compatibility with older versionsof GCC.
Older versions of GCC (prior to 4.9.0) incorrectly did not align astructure parameter on a 128-bit boundary when that structure containeda member requiring 128-bit alignment. This is corrected in morerecent versions of GCC. This option may be used to generate codethat is compatible with functions compiled with older versions ofGCC.
The-mno-compat-align-parm option is the default.
-mstack-protector-guard=guard ¶-mstack-protector-guard-reg=reg-mstack-protector-guard-offset=offsetGenerate stack protection code using canary atguard. Supportedlocations are ‘global’ for global canary or ‘tls’ for per-threadcanary in the TLS block (the default with GNU libc version 2.4 or later).
With the latter choice the options-mstack-protector-guard-reg=reg and-mstack-protector-guard-offset=offset furthermore specifywhich register to use as base register for reading the canary, and from whatoffset from that base register. The default for those is as specified in therelevant ABI.
-mpcrel ¶-mno-pcrelGenerate (do not generate) pc-relative addressing. The-mpcreloption requires that the medium code model (-mcmodel=medium)and prefixed addressing (-mprefixed) options are enabled.
-mprefixed ¶-mno-prefixedGenerate (do not generate) addressing modes using prefixed load andstore instructions. The-mprefixed option requires thatthe option-mcpu=power10 (or later) is enabled.
-mmma ¶-mno-mmaGenerate (do not generate) the MMA instructions. The-mmaoption requires that the option-mcpu=power10 (or later)is enabled.
-mrop-protect ¶-mno-rop-protectGenerate (do not generate) ROP protection instructions when the targetprocessor supports them. Currently this option disables the shrink-wrapoptimization (-fshrink-wrap).
-mprivileged ¶-mno-privilegedGenerate (do not generate) code that runs in privileged state.
-mblock-ops-unaligned-vsx ¶-mno-block-ops-unaligned-vsxGenerate (do not generate) unaligned vsx loads and stores forinline expansion ofmemcpy andmemmove.
-msplat-word-constant ¶-mno-splat-word-constantGenerate (do not generate) code that uses theXXSPLTIW instruction.This option is enabled by default.
-msplat-float-constant ¶-mno-splat-float-constantGenerate (do not generate) code that uses theXXSPLTIDP instruction.This option is enabled by default.
-mieee128-constant ¶-mno-ieee128-constantGenerate (do not generate) code that uses theLXVKQ instruction.This option is enabled by default.
-mwarn-altivec-long ¶-mno-warn-altivec-longEnable or disable warnings about deprecated ‘vector long ...’ Altivectype usage. This option is enabled by default.
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