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These command-line options are defined for RISC-V targets:
-mbranch-cost=n ¶Set the cost of branches to roughlyn instructions.
-mabi=ABI-string ¶Specify integer and floating-point calling convention.ABI-stringcontains two parts: the size of integer types and the registers used forfloating-point types. For example ‘-march=rv64ifd -mabi=lp64d’ means that‘long’ and pointers are 64-bit (implicitly defining ‘int’ to be32-bit), and that floating-point values up to 64 bits wide are passed in Fregisters. Contrast this with ‘-march=rv64ifd -mabi=lp64f’, which stillallows the compiler to generate code that uses the F and D extensions but onlyallows floating-point values up to 32 bits long to be passed in registers; or‘-march=rv64ifd -mabi=lp64’, in which no floating-point arguments arepassed in registers.
The default for this argument is system dependent; if you want a specificcalling convention you should specify one explicitly. The valid callingconventions are: ‘ilp32’, ‘ilp32f’, ‘ilp32d’, ‘lp64’,‘lp64f’, and ‘lp64d’. Some calling conventions are impossible toimplement on some ISAs: for example, ‘-march=rv32if -mabi=ilp32d’ isinvalid because the ABI requires 64-bit values be passed in F registers, but Fregisters are only 32 bits wide. There are also the ‘ilp32e’ ABI that canonly be used with the ‘rv32e’ architecture and the ‘lp64e’ ABI thatcan only be used with the ‘rv64e’. Those ABIs are not well-specified atpresent, and are subject to change.
-mfdiv ¶-mno-fdivDo or don’t use hardware floating-point divide and square root instructions.This requires the F or D extensions for floating-point registers. The defaultis to use them if the specified architecture has these instructions.
-mfence-tso ¶-mno-fence-tsoDo or don’t use the ‘fence.tso’ instruction, which is unimplemented onsome processors (including those from T-Head). If the ‘fence.tso’instruction is not available then a stronger fence is used instead.
-mdiv ¶-mno-divDo or don’t use hardware instructions for integer division. This requires theM extension. The default is to use them if the specified architecture hasthese instructions.
-misa-spec=ISA-spec-string ¶Specify the version of the RISC-V Unprivileged (formerly User-Level)ISA specification generated code should conform to. The possibilitiesforISA-spec-string are:
2.2Produce code conforming to version 2.2.
20190608Produce code conforming to version 20190608.
20191213Produce code conforming to version 20191213.
The default is-misa-spec=20191213 unless GCC has been configuredwith--with-isa-spec= specifying a different default version.
-march=[ISA|Profile|Profile_ISA|processor-string] ¶Generate code for given RISC-V ISA or profile or a combination of them(e.g. ‘rv64im’ ‘rvi20u64’ ‘rvi20u64_zbb’). The names ofISAs and profiles must be lower case.Examples include ‘rv64i’, ‘rv32g’,‘rv32e’, ‘rv32imaf’, ‘rva22u64’ and ‘rva23u64’.To combine a named profile with optional RISC-V ISA extensions,give the profile first and then append the extension name(s) usingan underscore as a delimiter (e.g.‘rvi20u64_zca_zcb’ ‘rva23u64_zacas’). Additionally, a special value‘help’ (-march=help) is accepted to list all supportedextensions.
-march=unset causes the compiler to ignore any-march=… optionsthat appear earlier on the command line, behaving as if the option was neverpassed. This is useful for ensuring that the architecture is taken from the-mcpu option, and an error results if no-mcpu optionis given when-march=unset is used.
The syntax of the ISA string is defined as follows:
Supported extensions are listed below:
| Extension Name | Supported Version | Description |
|---|---|---|
| ‘g’ | - | General-purpose computing base extension; ‘g’ expands to‘i’, ‘m’, ‘a’, ‘f’, ‘d’, ‘zicsr’ and‘zifencei’. |
| ‘e’ | 2.0 | Reduced base integer extension |
| ‘i’ | 2.0 2.1 | Base integer extension |
| ‘m’ | 2.0 | Integer multiplication and division extension |
| ‘a’ | 2.0 2.1 | Atomic extension |
| ‘f’ | 2.0 2.2 | Single-precision floating-point extension |
| ‘d’ | 2.0 2.2 | Double-precision floating-point extension |
| ‘c’ | 2.0 | Compressed extension |
| ‘b’ | 1.0 | Standard extension for bit manipulation functions |
| ‘v’ | 1.0 | Vector extension |
| ‘h’ | 1.0 | Hypervisor extension |
| ‘zic64b’ | 1.0 | Cache block size is 64 bytes |
| ‘zicbom’ | 1.0 | Cache-block management extension |
| ‘zicbop’ | 1.0 | Cache-block prefetch extension |
| ‘zicboz’ | 1.0 | Cache-block zero extension |
| ‘ziccamoa’ | 1.0 | Main memory supports all atomics in A |
| ‘ziccif’ | 1.0 | Main memory supports instruction fetch with atomicity requirement |
| ‘zicclsm’ | 1.0 | Main memory supports misaligned loads/stores |
| ‘ziccrse’ | 1.0 | Main memory supports forward progress on LR/SC sequences |
| ‘zicfilp’ | 1.0 | Control-flow integrity landing pad extension |
| ‘zicfiss’ | 1.0 | Control-flow integrity shadow stack extension |
| ‘zicntr’ | 2.0 | Standard extension for base counters and timers |
| ‘zicond’ | 1.0 | Integer conditional operations extension |
| ‘zicsr’ | 2.0 | Control and status register access extension |
| ‘zifencei’ | 2.0 | Instruction-fetch fence extension |
| ‘zihintntl’ | 1.0 | Non-temporal locality hints extension |
| ‘zihintpause’ | 2.0 | Pause hint extension |
| ‘zihpm’ | 2.0 | Standard extension for hardware performance counters |
| ‘zimop’ | 1.0 | May-be-operations extension |
| ‘zilsd’ | 1.0 | Load/store pair instructions extension |
| ‘zmmul’ | 1.0 | Integer multiplication extension |
| ‘za128rs’ | 1.0 | Reservation set size of 128 bytes |
| ‘za64rs’ | 1.0 | Reservation set size of 64 bytes |
| ‘zaamo’ | 1.0 | Atomic memory operations extension |
| ‘zabha’ | 1.0 | Byte and halfword atomic memory operations extension |
| ‘zacas’ | 1.0 | Atomic compare-and-swap instructions extension |
| ‘zalrsc’ | 1.0 | Load-reserved/store-conditional subset of the A extension |
| ‘zawrs’ | 1.0 | Wait-on-reservation-set extension |
| ‘zama16b’ | 1.0 | Misaligned loads, stores, and AMOs that are fully contained within a naturally-aligned 16-byte boundary are atomic |
| ‘zfa’ | 1.0 | Additional floating-point extension |
| ‘zfbfmin’ | 1.0 | Minimal BF16 support extension |
| ‘zfh’ | 1.0 | Half-precision floating-point extension |
| ‘zfhmin’ | 1.0 | Minimal half-precision floating-point extension |
| ‘zfinx’ | 1.0 | Single-precision floating-point in integer registers extension |
| ‘zdinx’ | 1.0 | Double-precision floating-point in integer registers extension |
| ‘zca’ | 1.0 | Integer compressed instruction extension |
| ‘zcb’ | 1.0 | Simple compressed instruction extension |
| ‘zcd’ | 1.0 | Compressed double-precision floating point loads and stores extension |
| ‘zce’ | 1.0 | Compressed instruction extensions for embedded processors |
| ‘zcf’ | 1.0 | Compressed single-precision floating point loads and stores extension |
| ‘zcmop’ | 1.0 | Compressed may-be-operations extension |
| ‘zcmp’ | 1.0 | Compressed push pop extension |
| ‘zcmt’ | 1.0 | Table jump instruction extension |
| ‘zclsd’ | 1.0 | Compressed load/store pair instructions extension |
| ‘zba’ | 1.0 | Address calculation extension |
| ‘zbb’ | 1.0 | Basic bit manipulation extension |
| ‘zbc’ | 1.0 | Carry-less multiplication extension |
| ‘zbkb’ | 1.0 | Cryptography bit-manipulation extension |
| ‘zbkc’ | 1.0 | Cryptography carry-less multiply extension |
| ‘zbkx’ | 1.0 | Cryptography crossbar permutation extension |
| ‘zbs’ | 1.0 | Single-bit operation extension |
| ‘zk’ | 1.0 | Standard scalar cryptography extension |
| ‘zkn’ | 1.0 | NIST algorithm suite extension |
| ‘zknd’ | 1.0 | AES Decryption extension |
| ‘zkne’ | 1.0 | AES Encryption extension |
| ‘zknh’ | 1.0 | Hash function extension |
| ‘zkr’ | 1.0 | Entropy source extension |
| ‘zks’ | 1.0 | ShangMi algorithm suite extension |
| ‘zksed’ | 1.0 | SM4 block cipher extension |
| ‘zksh’ | 1.0 | SM3 hash function extension |
| ‘zkt’ | 1.0 | Data independent execution latency extension |
| ‘ztso’ | 1.0 | Total store ordering extension |
| ‘zvbb’ | 1.0 | Vector basic bit-manipulation extension |
| ‘zvbc’ | 1.0 | Vector carry-less multiplication extension |
| ‘zve32f’ | 1.0 | Vector extensions for embedded processors |
| ‘zve32x’ | 1.0 | Vector extensions for embedded processors |
| ‘zve64d’ | 1.0 | Vector extensions for embedded processors |
| ‘zve64f’ | 1.0 | Vector extensions for embedded processors |
| ‘zve64x’ | 1.0 | Vector extensions for embedded processors |
| ‘zvfbfmin’ | 1.0 | Vector BF16 converts extension |
| ‘zvfbfwma’ | 1.0 | Vector BF16 widening multiply/add extension |
| ‘zvfh’ | 1.0 | Vector half-precision floating-point extension |
| ‘zvfhmin’ | 1.0 | Vector minimal half-precision floating-point extension |
| ‘zvkb’ | 1.0 | Vector cryptography bit-manipulation extension |
| ‘zvkg’ | 1.0 | Vector GCM/GMAC extension |
| ‘zvkn’ | 1.0 | Vector NIST Algorithm Suite extension, ‘zvkn’ will expand to |
| ‘zvknc’ | 1.0 | Vector NIST Algorithm Suite with carry-less multiply extension, ‘zvknc’ |
| ‘zvkned’ | 1.0 | Vector AES block cipher extension |
| ‘zvkng’ | 1.0 | Vector NIST Algorithm Suite with GCM extension, ‘zvkng’ will expand |
| ‘zvknha’ | 1.0 | Vector SHA-2 secure hash extension |
| ‘zvknhb’ | 1.0 | Vector SHA-2 secure hash extension |
| ‘zvks’ | 1.0 | Vector ShangMi algorithm suite extension, ‘zvks’ will expand |
| ‘zvksc’ | 1.0 | Vector ShangMi algorithm suite with carry-less multiplication extension, |
| ‘zvksed’ | 1.0 | Vector SM4 block cipher extension |
| ‘zvksg’ | 1.0 | Vector ShangMi algorithm suite with GCM extension |
| ‘zvksh’ | 1.0 | Vector SM3 secure hash extension |
| ‘zvkt’ | 1.0 | Vector data independent execution latency extension |
| ‘zvl1024b’ | 1.0 | Minimum vector length standard extensions |
| ‘zvl128b’ | 1.0 | Minimum vector length standard extensions |
| ‘zvl16384b’ | 1.0 | Minimum vector length standard extension |
| ‘zvl2048b’ | 1.0 | Minimum vector length standard extensions |
| ‘zvl256b’ | 1.0 | Minimum vector length standard extensions |
| ‘zvl32768b’ | 1.0 | Minimum vector length standard extension |
| ‘zvl32b’ | 1.0 | Minimum vector length standard extensions |
| ‘zvl4096b’ | 1.0 | Minimum vector length standard extensions |
| ‘zvl512b’ | 1.0 | Minimum vector length standard extensions |
| ‘zvl64b’ | 1.0 | Minimum vector length standard extensions |
| ‘zvl65536b’ | 1.0 | Minimum vector length standard extension |
| ‘zvl8192b’ | 1.0 | Minimum vector length standard extension |
| ‘zhinx’ | 1.0 | Half-precision floating-point in integer registers extension |
| ‘zhinxmin’ | 1.0 | Minimal half-precision floating-point in integer registers extension |
| ‘sdtrig’ | 1.0 | Debug triggers extension |
| ‘sha’ | 1.0 | The augmented hypervisor extension |
| ‘shcounterenw’ | 1.0 | Support writeable enables for any supported counter |
| ‘shgatpa’ | 1.0 | SvNNx4 mode supported for all modes supported by satp |
| ‘shlcofideleg’ | 1.0 | Delegating LCOFI interrupts to VS-mode |
| ‘shtvala’ | 1.0 | The htval register provides all needed values |
| ‘shvstvala’ | 1.0 | The vstval register provides all needed values |
| ‘shvstvecd’ | 1.0 | The vstvec register supports direct mode |
| ‘shvsatpa’ | 1.0 | The vsatp register supports all modes supported by satp |
| ‘smaia’ | 1.0 | Advanced interrupt architecture extension |
| ‘smcntrpmf’ | 1.0 | Cycle and instret privilege mode filtering |
| ‘smcsrind’ | 1.0 | Machine-level indirect CSR access |
| ‘smepmp’ | 1.0 | PMP enhancements for memory access and execution prevention on machine mode |
| ‘smmpm’ | 1.0 | Supervisor-mode pointer masking extension |
| ‘smnpm’ | 1.0 | Supervisor-mode pointer masking extension |
| ‘smrnmi’ | 1.0 | Resumable non-maskable interrupts |
| ‘smstateen’ | 1.0 | State enable extension |
| ‘smdbltrp’ | 1.0 | Double trap extensions |
| ‘ssaia’ | 1.0 | Advanced interrupt architecture extension for supervisor mode |
| ‘ssccptr’ | 1.0 | Main memory supports page table reads |
| ‘sscofpmf’ | 1.0 | Count overflow and filtering extension |
| ‘sscounterenw’ | 1.0 | Support writeable enables for any supported counter |
| ‘sscsrind’ | 1.0 | Supervisor-mode indirect CSR access |
| ‘ssnpm’ | 1.0 | Supervisor-mode pointer masking extension |
| ‘sspm’ | 1.0 | Supervisor-mode pointer masking extension |
| ‘ssstateen’ | 1.0 | Supervisor-mode state-enable extension |
| ‘sstc’ | 1.0 | Supervisor-mode timer interrupts extension |
| ‘sstvala’ | 1.0 | Stval provides all needed values |
| ‘sstvecd’ | 1.0 | Stvec supports direct mode |
| ‘ssstrict’ | 1.0 | Unimplemented reserved encodings raise illegal instruction exceptions and no non-conforming extensions are present |
| ‘ssdbltrp’ | 1.0 | Double trap extensions |
| ‘ssu64xl’ | 1.0 | UXLEN=64 must be supported |
| ‘supm’ | 1.0 | User-mode pointer masking extension |
| ‘svinval’ | 1.0 | Fine-grained address-translation cache invalidation extension |
| ‘svnapot’ | 1.0 | NAPOT translation contiguity extension |
| ‘svpbmt’ | 1.0 | Page-based memory types extension |
| ‘svvptc’ | 1.0 | Extension for obviating memory-management instructions after marking PTEs valid |
| ‘svadu’ | 1.0 | Hardware updating of A/D bits extension |
| ‘svade’ | 1.0 | Cause exception when hardware updating of A/D bits is disabled |
| ‘svbare’ | 1.0 | Satp mode bare is supported |
| ‘xcvalu’ | 1.0 | Core-V miscellaneous ALU extension |
| ‘xcvbi’ | 1.0 | Core-V immediate branch extension |
| ‘xcvelw’ | 1.0 | Core-V event load word extension |
| ‘xcvmac’ | 1.0 | Core-V multiply-accumulate extension |
| ‘xcvsimd’ | 1.0 | Core-V SIMD extension |
| ‘xsfcease’ | 1.0 | SiFive CEASE instruction extension |
| ‘xsfvcp’ | 1.0 | SiFive VCIX vector coprocessor extension |
| ‘xsfvfnrclipxfqf’ | 1.0 | SiFive FP32-to-int8 ranged clip instructions |
| ‘xsfvqmaccdod’ | 1.0 | SiFive int8 matrix multiplication extension |
| ‘xsfvqmaccqoq’ | 1.0 | SiFive int8 matrix multiplication extension |
| ‘xtheadba’ | 1.0 | T-head address calculation extension |
| ‘xtheadbb’ | 1.0 | T-head basic bit-manipulation extension |
| ‘xtheadbs’ | 1.0 | T-head single-bit instructions extension |
| ‘xtheadcmo’ | 1.0 | T-head cache management operations extension |
| ‘xtheadcondmov’ | 1.0 | T-head conditional move extension |
| ‘xtheadfmemidx’ | 1.0 | T-head indexed memory operations for floating-point registers extension |
| ‘xtheadfmv’ | 1.0 | T-head double floating-point high-bit data transmission extension |
| ‘xtheadint’ | 1.0 | T-head acceleration interruption extension |
| ‘xtheadmac’ | 1.0 | T-head multiply-accumulate extension |
| ‘xtheadmemidx’ | 1.0 | T-head indexed memory operation extension |
| ‘xtheadmempair’ | 1.0 | T-head two-GPR memory operation extension |
| ‘xtheadsync’ | 1.0 | T-head multi-core synchronization extension |
| ‘xtheadvector’ | 1.0 | T-head vector extension |
| ‘xventanacondops’ | 1.0 | Ventana integer conditional operations extension |
| ‘xmipscmov’ | 1.0 | Mips conditional move extension |
| ‘xmipscbop’ | 1.0 | Mips prefetch extension |
| ‘xandesperf’ | 5.0 | Andes performace extension |
| ‘xandesbfhcvt’ | 5.0 | Andes bfloat16 conversion extension |
| ‘xandesvbfhcvt’ | 5.0 | Andes vector bfloat16 conversion extension |
| ‘xandesvsintload’ | 5.0 | Andes vector INT4 load extension |
| ‘xandesvpackfph’ | 5.0 | Andes vector packed FP16 extension |
| ‘xandesvdot’ | 5.0 | Andes vector dot product extension |
| ‘xsmtvdot’ | 1.0 | SpacemiT vector dot product extension |
When-march= is not specified, GCC uses the setting from-mcpu.
If both-march and-mcpu= are not specified, the default forthis argument is system dependent; if you want a specific architectureextension, you should specify one explicitly.
When the RISC-V specifications define an extension as depending on otherextensions, GCC implicitly adds the dependent extensions to the enabledextension set if they weren’t added explicitly.
‘Core Name’
-mcpu=processor-string ¶Use architecture of and optimize the output for the given processor, specifiedby particular CPU name. Permissible values for this option are:
‘sifive-e20’,
‘sifive-e21’,
‘sifive-e24’,
‘sifive-e31’,
‘sifive-e34’,
‘sifive-e76’,
‘sifive-s21’,
‘sifive-s51’,
‘sifive-s54’,
‘sifive-s76’,
‘sifive-u54’,
‘sifive-u74’,
‘sifive-x280’,
‘sifive-p450’,
‘sifive-p670’,
‘thead-c906’,
‘xt-c908’,
‘xt-c908v’,
‘xt-c910’,
‘xt-c910v2’,
‘xt-c920’,
‘xt-c920v2’,
‘tt-ascalon-d8’,
‘xiangshan-nanhu’,
‘xiangshan-kunminghu’,
‘mips-p8700’,
‘andes-n22’,
‘andes-n25’,
‘andes-a25’,
‘andes-nx25’,
‘andes-ax25’,
‘andes-a27’,
‘andes-ax27’,
‘andes-n225’,
‘andes-d23’,
‘andes-n45’,
‘andes-nx45’,
‘andes-a45’,
‘andes-ax45’,
‘spacemit-x60’.
Note that-mcpu does not override-march or-mtune.
‘Tune Name’
-mtune=processor-string ¶Optimize the output for the given processor, specified by microarchitecture orparticular CPU name. Permissible values for this option are:
‘generic’,
‘rocket’,
‘sifive-3-series’,
‘sifive-5-series’,
‘sifive-7-series’,
‘sifive-p400-series’,
‘sifive-p600-series’,
‘tt-ascalon-d8’,
‘thead-c906’,
‘xt-c908’,
‘xt-c908v’,
‘xt-c910’,
‘xt-c910v2’,
‘xt-c920’,
‘xt-c920v2’,
‘xiangshan-nanhu’,
‘xiangshan-kunminghu’,
‘spacemit-x60’,
‘generic-ooo’,
‘size’,
‘mips-p8700’,
‘andes-25-series’,
‘andes-23-series’,
‘andes-45-series’,
and all valid options for-mcpu=.
When-mtune= is not specified, GCC uses the setting from-mcpu. The default is ‘generic’ if neither is specified.
The ‘size’ choice is not intended for use by end-users. This is usedwhen-Os is specified. It overrides the instruction cost infoprovided by-mtune=, but does not override the pipeline info. Thishelps reduce code size while still giving good performance.
-mpreferred-stack-boundary=num ¶Attempt to keep the stack boundary aligned to a 2 raised tonumbyte boundary. If-mpreferred-stack-boundary is not specified,the default is 4 (16 bytes or 128-bits).
Warning: If you use this switch, then you must build all modules withthe same value, including any libraries. This includes the system librariesand startup modules.
-msmall-data-limit=n ¶Put global and static data smaller thann bytes into a special section(on some targets).
-msave-restore ¶-mno-save-restoreDo or don’t use smaller but slower prologue and epilogue code that useslibrary function calls. The default is to use fast inline prologues andepilogues.
-mmovcc ¶-mno-movccDo or don’t produce branchless conditional-move code sequences even withtargets that do not have specific instructions for conditional operations.If enabled, sequences of ALU operations are produced using base integerISA instructions where profitable.
-minline-atomics ¶-mno-inline-atomicsDo or don’t use smaller but slower subword atomic emulation code that useslibatomic function calls. The default is to use fast inline subword atomicsthat do not require libatomic.
-minline-strlen ¶-mno-inline-strlenDo or do not attempt to inlinestrlen calls if possible.Inlining can only be done if the string is properly alignedand instructions for accelerated processing are available.The default is to inlinestrlen calls.
-minline-strcmp ¶-mno-inline-strcmpDo or do not attempt to inlinestrcmp calls if possible.Inlining can only be done if the strings are properly alignedand instructions for accelerated processing are available.The default is to inlinestrcmp calls.
-minline-strncmp ¶-mno-inline-strncmpDo or do not attempt to inlinestrncmp calls if possible.Inlining can only be done if the strings are properly alignedand instructions for accelerated processing are available.The default is to inlinestrncmp calls.
-mstringop-strategy=strategy ¶Specify a particular strategy for inlining string and memory operations.strategy may be one of ‘auto’, ‘libcall’, ‘scalar’,or ‘vector’.
-mshorten-memrefs ¶-mno-shorten-memrefsDo or do not attempt to make more use of compressed load/store instructions byreplacing a load/store of ’base register + large offset’ with a new load/storeof ’new base + small offset’. If the new base gets stored in a compressedregister, then the new load/store can be compressed. Currently targets 32-bitinteger load/stores only.
-mstrict-align ¶-mno-strict-alignDo not or do generate unaligned memory accesses. The default is set dependingon whether the processor we are optimizing for supports fast unaligned accessor not.
-mscalar-strict-align ¶-mno-scalar-strict-alignDo not or do generate unaligned memory accesses. The default is set dependingon whether the processor we are optimizing for supports fast unaligned accessor not. This is an alias for-mstrict-align.
-mvector-strict-align ¶-mno-vector-strict-alignDo not or do generate unaligned vector memory accesses. The default is setto off unless the processor we are optimizing for explicitly supportselement-misaligned vector memory access.
-mmax-vectorization ¶-mno-max-vectorizationEnable or disable an override to vectorizer cost model making vectorizationalways appear profitable. Unlike-fno-vect-cost-model or-fvect-cost-model=unlimited this option does not turn off costcomparison between different vector modes.
-mcmodel=medlow ¶Generate code for the medium-low code model. The program and its staticallydefined symbols must lie within a single 2 GiB address range and must liebetween absolute addresses −2 GiB and +2 GiB. Programs can be staticallyor dynamically linked. This is the default code model unless GCC has beenconfigured with--with-cmodel= specifying a different default codemodel.
-mcmodel=medany ¶Generate code for the medium-any code model. The program and its staticallydefined symbols must be within any single 2 GiB address range. Programs can bestatically or dynamically linked.
The code generated by the medium-any code model is position-independent, but isnot guaranteed to function correctly when linked into position-independentexecutables or libraries.
-mcmodel=large ¶Generate code for a large code model, which has no restrictions on size orplacement of symbols.
-mexplicit-relocs ¶-mno-explicit-relocsUse or do not use assembler relocation operators when dealing with symbolicaddresses. The alternative is to use assembler macros instead, which maylimit optimization.
-mrelax ¶-mno-relaxTake advantage of linker relaxations to reduce the number of instructionsrequired to materialize symbol addresses. The default is to take advantage oflinker relaxations.
-mriscv-attribute ¶-mno-riscv-attributeEmit (do not emit) RISC-V attribute to record extra information into ELFobjects. This feature requires at least binutils 2.32.
-mcsr-check ¶-mno-csr-checkEnables or disables the CSR checking.
-momit-leaf-frame-pointer ¶Don’t keep the frame pointer in a register for leaf functions. Thisavoids the instructions to save, set up and restore frame pointers andmakes an extra register available in leaf functions.
-malign-data=type ¶Control how GCC aligns variables and constants of array, structure, or uniontypes. Supported values fortype are ‘xlen’ which uses x registerwidth as the alignment value, and ‘natural’ which uses natural alignment.‘xlen’ is the default.
-mbig-endian ¶Generate big-endian code. This is the default when GCC is configured for a‘riscv64be-*-*’ or ‘riscv32be-*-*’ target.
-mlittle-endian ¶Generate little-endian code. This is the default when GCC is configured for a‘riscv64-*-*’ or ‘riscv32-*-*’ but not a ‘riscv64be-*-*’ or‘riscv32be-*-*’ target.
-mstack-protector-guard=guard ¶-mstack-protector-guard-reg=reg-mstack-protector-guard-offset=offsetGenerate stack protection code using canary atguard. Supportedlocations are ‘global’ for a global canary or ‘tls’ for per-threadcanary in the TLS block.
With the latter choice the options-mstack-protector-guard-reg=reg and-mstack-protector-guard-offset=offset furthermore specifywhich register to use as base register for reading the canary,and from what offset from that base register. There is no defaultregister or offset as this is entirely for use within the Linuxkernel.
-mtls-dialect=desc ¶Use TLS descriptors as the thread-local storage mechanism for dynamic accessesof TLS variables.
-mtls-dialect=trad ¶Use traditional TLS as the thread-local storage mechanism for dynamic accessesof TLS variables. This is the default.
-mrvv-vector-bits=value ¶Specify how the number of bits for an RVV vector register, as taken fromthe-march= option, is interpreted.Thevalue parameter is specified as a string keyword and may be one of‘scalable’ or ‘zvl’. The default is ‘scalable’, which tellsGCC to interpret the number as a minimum, while ‘zvl’ tells GCC to useexactly the number of bits specified.
-mrvv-max-lmul=value ¶This option allows explicit control over the maximum length multiplier (LMUL)used when generating code for the RISC-V Vector Extensions (RVV).Thevalue parameter is specified as a string keyword and may beone of ‘m1’, ‘m2’, ‘m4’, ‘m8’, or ‘dynamic’. Thedefault is ‘m1’ for compatibility with existing hardware that does notsupport the other options.
-madjust-lmul-cost ¶-mno-adjust-lmul-costThis option adjusts the cost model used to schedule vector instructions tomultiply the latency of instructions by the RVV length multiplier, LMUL.It is disabled by default.
-mautovec-segment ¶-mno-autovec-segmentEnable or disable generation of vector segment load/store instructions.This option is enabled by default.
Next:RL78 Options, Previous:PRU Options, Up:Machine-Dependent Options [Contents][Index]