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7.13.24.5 PowerPC AltiVec Built-in Functions Available on ISA 3.1 ¶

The following additional built-in functions are also available for thePowerPC family of processors, starting with ISA 3.1 (-mcpu=power10):

int vec_test_lsbb_all_ones (vector signed char);

int vec_test_lsbb_all_ones (vector unsigned char);

int vec_test_lsbb_all_ones (vector bool char);

The builtinvec_test_lsbb_all_ones returns 1 if the least significantbit in each byte is equal to 1. It returns 0 otherwise.

int vec_test_lsbb_all_zeros (vector signed char);

int vec_test_lsbb_all_zeros (vector unsigned char);

int vec_test_lsbb_all_zeros (vector bool char);

The builtinvec_test_lsbb_all_zeros returns 1 if the least significantbit in each byte is equal to zero. It returns 0 otherwise.

vector unsigned long long int

vec_cfuge (vector unsigned long long int, vector unsigned long long int);

Perform a vector centrifuge operation, as if implemented by thevcfuged instruction.

vector unsigned long long int

vec_cntlzm (vector unsigned long long int, vector unsigned long long int);

Perform a vector count leading zeros under bit mask operation, as ifimplemented by thevclzdm instruction.

vector unsigned long long int

vec_cnttzm (vector unsigned long long int, vector unsigned long long int);

Perform a vector count trailing zeros under bit mask operation, as ifimplemented by thevctzdm instruction.

vector signed char

vec_clrl (vector signed chara, unsigned intn);

vector unsigned char

vec_clrl (vector unsigned chara, unsigned intn);

Clear the left-most(16 - n) bytes of vector argumenta, as ifimplemented by thevclrlb instruction on a big-endian targetand by thevclrrb instruction on a little-endian target. Avalue ofn that is greater than 16 is treated as if it equaled 16.

vector signed char

vec_clrr (vector signed chara, unsigned intn);

vector unsigned char

vec_clrr (vector unsigned chara, unsigned intn);

Clear the right-most(16 - n) bytes of vector argumenta, as ifimplemented by thevclrrb instruction on a big-endian targetand by thevclrlb instruction on a little-endian target. Avalue ofn that is greater than 16 is treated as if it equaled 16.

vector unsigned long long int

vec_gnb (vector unsigned __int128, const unsigned char);

Perform a 128-bit vector gather operation, as if implemented by thevgnb instruction. The second argument must be a literalinteger value between 2 and 7 inclusive.

Vector Extract

vector unsigned long long int

vec_extractl (vector unsigned char, vector unsigned char, unsigned int);

vector unsigned long long int

vec_extractl (vector unsigned short, vector unsigned short, unsigned int);

vector unsigned long long int

vec_extractl (vector unsigned int, vector unsigned int, unsigned int);

vector unsigned long long int

vec_extractl (vector unsigned long long, vector unsigned long long, unsigned int);

Extract an element from two concatenated vectors starting at the given byte indexin natural-endian order, and place it zero-extended in doubleword 1 of the resultaccording to natural element order. If the byte index is out of range for thedata type, the intrinsic will be rejected.For little-endian, this output will match the placement by the hardwareinstruction, i.e., dword[0] in RTL notation. For big-endian, an additionalinstruction is needed to move it from the "left" doubleword to the "right" one.For little-endian, semantics matching thevextdubvrx,vextduhvrx,vextduwvrx instruction will be generated, while forbig-endian, semantics matching thevextdubvlx,vextduhvlx,vextduwvlx instructionswill be generated. Note that some fairly anomalous results can be generated ifthe byte index is not aligned on an element boundary for the element beingextracted. This is a limitation of the bi-endian vector programming model isconsistent with the limitation onvec_perm.

vector unsigned long long int

vec_extracth (vector unsigned char, vector unsigned char, unsigned int);

vector unsigned long long int

vec_extracth (vector unsigned short, vector unsigned short,

unsigned int);

vector unsigned long long int

vec_extracth (vector unsigned int, vector unsigned int, unsigned int);

vector unsigned long long int

vec_extracth (vector unsigned long long, vector unsigned long long,

unsigned int);

Extract an element from two concatenated vectors starting at the given byteindex. The index is based on big endian order for a little endian system.Similarly, the index is based on little endian order for a big endian system.The extraced elements are zero-extended and put in doubleword 1according to natural element order. If the byte index is out of range for thedata type, the intrinsic will be rejected. For little-endian, this outputwill match the placement by the hardware instruction (vextdubvrx, vextduhvrx,vextduwvrx, vextddvrx) i.e., dword[0] in RTLnotation. For big-endian, an additional instruction is needed to move itfrom the "left" doubleword to the "right" one. For little-endian, semanticsmatching thevextdubvlx,vextduhvlx,vextduwvlxinstructions will be generated, while for big-endian, semantics matching thevextdubvrx,vextduhvrx,vextduwvrx instructions willbe generated. Note that some fairly anomalousresults can be generated if the byte index is not aligned on theelement boundary for the element being extracted. This is alimitation of the bi-endian vector programming model consistent with thelimitation onvec_perm.

vector unsigned long long int

vec_pdep (vector unsigned long long int, vector unsigned long long int);

Perform a vector parallel bits deposit operation, as if implemented bythevpdepd instruction.

Vector Insert

vector unsigned char

vec_insertl (unsigned char, vector unsigned char, unsigned int);

vector unsigned short

vec_insertl (unsigned short, vector unsigned short, unsigned int);

vector unsigned int

vec_insertl (unsigned int, vector unsigned int, unsigned int);

vector unsigned long long

vec_insertl (unsigned long long, vector unsigned long long,

unsigned int);

vector unsigned char

vec_insertl (vector unsigned char, vector unsigned char, unsigned int;

vector unsigned short

vec_insertl (vector unsigned short, vector unsigned short,

unsigned int);

vector unsigned int

vec_insertl (vector unsigned int, vector unsigned int, unsigned int);

Let src be the first argument, when the first argument is a scalar, or therightmost element of the left doubleword of the first argument, when the firstargument is a vector. Insert the source into the destination at the positiongiven by the third argument, using natural element order in the secondargument. The rest of the second argument is unchanged. If the byteindex is greater than 14 for halfwords, greater than 12 for words, orgreater than 8 for doublewords the result is undefined. For little-endian,the generated code will be semantically equivalent tovins[bhwd]rxinstructions. Similarly for big-endian it will be semantically equivalenttovins[bhwd]lx. Note that some fairly anomalous results can begenerated if the byte index is not aligned on an element boundary for thetype of element being inserted.

vector unsigned char

vec_inserth (unsigned char, vector unsigned char, unsigned int);

vector unsigned short

vec_inserth (unsigned short, vector unsigned short, unsigned int);

vector unsigned int

vec_inserth (unsigned int, vector unsigned int, unsigned int);

vector unsigned long long

vec_inserth (unsigned long long, vector unsigned long long,

unsigned int);

vector unsigned char

vec_inserth (vector unsigned char, vector unsigned char, unsigned int);

vector unsigned short

vec_inserth (vector unsigned short, vector unsigned short,

unsigned int);

vector unsigned int

vec_inserth (vector unsigned int, vector unsigned int, unsigned int);

Let src be the first argument, when the first argument is a scalar, or therightmost element of the first argument, when the first argument is a vector.Insert src into the second argument at the position identified by the thirdargument, using opposite element order in the second argument, and leaving therest of the second argument unchanged. If the byte index is greater than 14for halfwords, 12 for words, or 8 for doublewords, the intrinsic will berejected. Note that the underlying hardware instruction uses the same registerfor the second argument and the result.For little-endian, the code generation will be semantically equivalent tovins[bhwd]lx, while for big-endian it will be semantically equivalent tovins[bhwd]rx.Note that some fairly anomalous results can be generated if the byte index isnot aligned on an element boundary for the sort of element being inserted.

Vector Replace Element

vector signed int vec_replace_elt (vector signed int, signed int,

const int);

vector unsigned int vec_replace_elt (vector unsigned int,

unsigned int, const int);

vector float vec_replace_elt (vector float, float, const int);

vector signed long long vec_replace_elt (vector signed long long,

signed long long, const int);

vector unsigned long long vec_replace_elt (vector unsigned long long,

unsigned long long, const int);

vector double rec_replace_elt (vector double, double, const int);

The third argument (constrained to [0,3]) identifies the natural-endianelement number of the first argument that will be replaced by the secondargument to produce the result. The other elements of the first argument willremain unchanged in the result.

If it’s desirable to insert a word at an unaligned position, usevec_replace_unaligned instead.

Vector Replace Unaligned

vector unsigned char vec_replace_unaligned (vector unsigned char,

signed int, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char,

unsigned int, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char,

float, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char,

signed long long, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char,

unsigned long long, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char,

double, const int);

The second argument replaces a portion of the first argument to produce theresult, with the rest of the first argument unchanged in the result. Thethird argument identifies the byte index (using left-to-right, or big-endianorder) where the high-order byte of the second argument will be placed, withthe remaining bytes of the second argument placed naturally "to the right"of the high-order byte.

The programmer is responsible for understanding the endianness issues involvedwith the first argument and the result.

Vector Shift Left Double Bit Immediate

vector signed char vec_sldb (vector signed char, vector signed char,

const unsigned int);

vector unsigned char vec_sldb (vector unsigned char,

vector unsigned char, const unsigned int);

vector signed short vec_sldb (vector signed short, vector signed short,

const unsigned int);

vector unsigned short vec_sldb (vector unsigned short,

vector unsigned short, const unsigned int);

vector signed int vec_sldb (vector signed int, vector signed int,

const unsigned int);

vector unsigned int vec_sldb (vector unsigned int, vector unsigned int,

const unsigned int);

vector signed long long vec_sldb (vector signed long long,

vector signed long long, const unsigned int);

vector unsigned long long vec_sldb (vector unsigned long long,

vector unsigned long long, const unsigned int);

vector signed __int128 vec_sldb (vector signed __int128,

vector signed __int128, const unsigned int);

vector unsigned __int128 vec_sldb (vector unsigned __int128,

vector unsigned __int128, const unsigned int);

Shift the combined input vectors left by the amount specified by the low-orderthree bits of the third argument, and return the leftmost remaining 128 bits.Code using this instruction must be endian-aware.

Vector Shift Right Double Bit Immediate

vector signed char vec_srdb (vector signed char, vector signed char,

const unsigned int);

vector unsigned char vec_srdb (vector unsigned char, vector unsigned char,

const unsigned int);

vector signed short vec_srdb (vector signed short, vector signed short,

const unsigned int);

vector unsigned short vec_srdb (vector unsigned short, vector unsigned short,

const unsigned int);

vector signed int vec_srdb (vector signed int, vector signed int,

const unsigned int);

vector unsigned int vec_srdb (vector unsigned int, vector unsigned int,

const unsigned int);

vector signed long long vec_srdb (vector signed long long,

vector signed long long, const unsigned int);

vector unsigned long long vec_srdb (vector unsigned long long,

vector unsigned long long, const unsigned int);

vector signed __int128 vec_srdb (vector signed __int128,

vector signed __int128, const unsigned int);

vector unsigned __int128 vec_srdb (vector unsigned __int128,

vector unsigned __int128, const unsigned int);

Shift the combined input vectors right by the amount specified by the low-orderthree bits of the third argument, and return the remaining 128 bits. Codeusing this built-in must be endian-aware.

Vector Splat

vector signed int vec_splati (const signed int);

vector float vec_splati (const float);

Splat a 32-bit immediate into a vector of words.

vector double vec_splatid (const float);

Convert a single precision floating-point value to double-precision and splatthe result to a vector of double-precision floats.

vector signed int vec_splati_ins (vector signed int,

const unsigned int, const signed int);

vector unsigned int vec_splati_ins (vector unsigned int,

const unsigned int, const unsigned int);

vector float vec_splati_ins (vector float, const unsigned int,

const float);

Argument 2 must be either 0 or 1. Splat the value of argument 3 into the wordidentified by argument 2 of each doubleword of argument 1 and return theresult. The other words of argument 1 are unchanged.

Vector Blend Variable

vector signed char vec_blendv (vector signed char, vector signed char,

vector unsigned char);

vector unsigned char vec_blendv (vector unsigned char,

vector unsigned char, vector unsigned char);

vector signed short vec_blendv (vector signed short,

vector signed short, vector unsigned short);

vector unsigned short vec_blendv (vector unsigned short,

vector unsigned short, vector unsigned short);

vector signed int vec_blendv (vector signed int, vector signed int,

vector unsigned int);

vector unsigned int vec_blendv (vector unsigned int,

vector unsigned int, vector unsigned int);

vector signed long long vec_blendv (vector signed long long,

vector signed long long, vector unsigned long long);

vector unsigned long long vec_blendv (vector unsigned long long,

vector unsigned long long, vector unsigned long long);

vector float vec_blendv (vector float, vector float,

vector unsigned int);

vector double vec_blendv (vector double, vector double,

vector unsigned long long);

Blend the first and second argument vectors according to the sign bits of thecorresponding elements of the third argument vector. This is similar to thevsel andxxsel instructions but for bigger elements.

Vector Permute Extended

vector signed char vec_permx (vector signed char, vector signed char,

vector unsigned char, const int);

vector unsigned char vec_permx (vector unsigned char,

vector unsigned char, vector unsigned char, const int);

vector signed short vec_permx (vector signed short,

vector signed short, vector unsigned char, const int);

vector unsigned short vec_permx (vector unsigned short,

vector unsigned short, vector unsigned char, const int);

vector signed int vec_permx (vector signed int, vector signed int,

vector unsigned char, const int);

vector unsigned int vec_permx (vector unsigned int,

vector unsigned int, vector unsigned char, const int);

vector signed long long vec_permx (vector signed long long,

vector signed long long, vector unsigned char, const int);

vector unsigned long long vec_permx (vector unsigned long long,

vector unsigned long long, vector unsigned char, const int);

vector float (vector float, vector float, vector unsigned char,

const int);

vector double (vector double, vector double, vector unsigned char,

const int);

Perform a partial permute of the first two arguments, which form a 32-bytesection of an emulated vector up to 256 bytes wide, using the partial permutecontrol vector in the third argument. The fourth argument (constrained tovalues of 0-7) identifies which 32-byte section of the emulated vector iscontained in the first two arguments.

vector unsigned long long int

vec_pext (vector unsigned long long int, vector unsigned long long int);

Perform a vector parallel bit extract operation, as if implemented bythevpextd instruction.

vector unsigned char vec_stril (vector unsigned char);

vector signed char vec_stril (vector signed char);

vector unsigned short vec_stril (vector unsigned short);

vector signed short vec_stril (vector signed short);

Isolate the left-most non-zero elements of the incoming vector argument,replacing all elements to the right of the left-most zero elementfound within the argument with zero. The typical implementation usesthevstribl orvstrihl instruction on big-endian targetsand uses thevstribr orvstrihr instruction onlittle-endian targets.

int vec_stril_p (vector unsigned char);

int vec_stril_p (vector signed char);

int short vec_stril_p (vector unsigned short);

int vec_stril_p (vector signed short);

Return a non-zero value if and only if the argument contains a zeroelement. The typical implementation usesthevstribl. orvstrihl. instruction on big-endian targetsand uses thevstribr. orvstrihr. instruction onlittle-endian targets. Choose this built-in to check for presence ofzero element if the same argument is also passed tovec_stril.

vector unsigned char vec_strir (vector unsigned char);

vector signed char vec_strir (vector signed char);

vector unsigned short vec_strir (vector unsigned short);

vector signed short vec_strir (vector signed short);

Isolate the right-most non-zero elements of the incoming vector argument,replacing all elements to the left of the right-most zero elementfound within the argument with zero. The typical implementation usesthevstribr orvstrihr instruction on big-endian targetsand uses thevstribl orvstrihl instruction onlittle-endian targets.

int vec_strir_p (vector unsigned char);

int vec_strir_p (vector signed char);

int short vec_strir_p (vector unsigned short);

int vec_strir_p (vector signed short);

Return a non-zero value if and only if the argument contains a zeroelement. The typical implementation usesthevstribr. orvstrihr. instruction on big-endian targetsand uses thevstribl. orvstrihl. instruction onlittle-endian targets. Choose this built-in to check for presence ofzero element if the same argument is also passed tovec_strir.

vector unsigned char

vec_ternarylogic (vector unsigned char, vector unsigned char,

            vector unsigned char, const unsigned int);

vector unsigned short

vec_ternarylogic (vector unsigned short, vector unsigned short,

            vector unsigned short, const unsigned int);

vector unsigned int

vec_ternarylogic (vector unsigned int, vector unsigned int,

            vector unsigned int, const unsigned int);

vector unsigned long long int

vec_ternarylogic (vector unsigned long long int, vector unsigned long long int,

            vector unsigned long long int, const unsigned int);

vector unsigned __int128

vec_ternarylogic (vector unsigned __int128, vector unsigned __int128,

            vector unsigned __int128, const unsigned int);

Perform a 128-bit vector evaluate operation, as if implemented by thexxeval instruction. The fourth argument must be a literalinteger value between 0 and 255 inclusive.

vector unsigned char vec_genpcvm (vector unsigned char, const int);

vector unsigned short vec_genpcvm (vector unsigned short, const int);

vector unsigned int vec_genpcvm (vector unsigned int, const int);

vector unsigned int vec_genpcvm (vector unsigned long long int,

                                         const int);

Vector Integer Multiply/Divide/Modulo

vector signed int

vec_mulh (vector signed inta, vector signed intb);

vector unsigned int

vec_mulh (vector unsigned inta, vector unsigned intb);

For each integer valuei from 0 to 3, do the following. The integervalue in word elementi of a is multiplied by the integer value in wordelementi of b. The high-order 32 bits of the 64-bit product are placedinto word elementi of the vector returned.

vector signed long long

vec_mulh (vector signed long longa, vector signed long longb);

vector unsigned long long

vec_mulh (vector unsigned long longa, vector unsigned long longb);

For each integer valuei from 0 to 1, do the following. The integervalue in doubleword elementi of a is multiplied by the integer value indoubleword elementi of b. The high-order 64 bits of the 128-bit productare placed into doubleword elementi of the vector returned.

vector unsigned long long

vec_mul (vector unsigned long longa, vector unsigned long longb);

vector signed long long

vec_mul (vector signed long longa, vector signed long longb);

For each integer valuei from 0 to 1, do the following. The integervalue in doubleword elementi of a is multiplied by the integer value indoubleword elementi of b. The low-order 64 bits of the 128-bit productare placed into doubleword elementi of the vector returned.

vector signed int

vec_div (vector signed inta, vector signed intb);

vector unsigned int

vec_div (vector unsigned inta, vector unsigned intb);

For each integer valuei from 0 to 3, do the following. The integer inword elementi of a is divided by the integer in word elementiof b. The unique integer quotient is placed into the word elementi ofthe vector returned. If an attempt is made to perform any of the divisions<anything> ÷ 0 then the quotient is undefined.

vector signed long long

vec_div (vector signed long longa, vector signed long longb);

vector unsigned long long

vec_div (vector unsigned long longa, vector unsigned long longb);

For each integer valuei from 0 to 1, do the following. The integer indoubleword elementi of a is divided by the integer in doublewordelementi of b. The unique integer quotient is placed into thedoubleword elementi of the vector returned. If an attempt is made toperform any of the divisions 0x8000_0000_0000_0000 ÷ -1 or <anything> ÷ 0 thenthe quotient is undefined.

vector signed int

vec_dive (vector signed inta, vector signed intb);

vector unsigned int

vec_dive (vector unsigned inta, vector unsigned intb);

For each integer valuei from 0 to 3, do the following. The integer inword elementi of a is shifted left by 32 bits, then divided by theinteger in word elementi of b. The unique integer quotient is placedinto the word elementi of the vector returned. If the quotient cannotbe represented in 32 bits, or if an attempt is made to perform any of thedivisions <anything> ÷ 0 then the quotient is undefined.

vector signed long long

vec_dive (vector signed long longa, vector signed long longb);

vector unsigned long long

vec_dive (vector unsigned long longa, vector unsigned long longb);

For each integer valuei from 0 to 1, do the following. The integer indoubleword elementi of a is shifted left by 64 bits, then divided bythe integer in doubleword elementi of b. The unique integer quotient isplaced into the doubleword elementi of the vector returned. If thequotient cannot be represented in 64 bits, or if an attempt is made to perform<anything> ÷ 0 then the quotient is undefined.

vector signed int

vec_mod (vector signed inta, vector signed intb);

vector unsigned int

vec_mod (vector unsigned inta, vector unsigned intb);

For each integer valuei from 0 to 3, do the following. The integer inword elementi of a is divided by the integer in word elementiof b. The unique integer remainder is placed into the word elementi ofthe vector returned. If an attempt is made to perform any of the divisions0x8000_0000 ÷ -1 or <anything> ÷ 0 then the remainder is undefined.

vector signed long long

vec_mod (vector signed long longa, vector signed long longb);

vector unsigned long long

vec_mod (vector unsigned long longa, vector unsigned long longb);

For each integer valuei from 0 to 1, do the following. The integer indoubleword elementi of a is divided by the integer in doublewordelementi of b. The unique integer remainder is placed into thedoubleword elementi of the vector returned. If an attempt is made toperform <anything> ÷ 0 then the remainder is undefined.

Generate PCV from specified Mask size, as if implemented by thexxgenpcvbm,xxgenpcvhm,xxgenpcvwm instructions, whereimmediate value is either 0, 1, 2 or 3.

vector unsigned __int128 vec_rl (vector unsigned __int128A,

                                         vector unsigned __int128B);

vector signed __int128 vec_rl (vector signed __int128A,

                                       vector unsigned __int128B);

Result value: Each element ofR is obtained by rotating the corresponding elementofA left by the number of bits specified by the corresponding element ofB.

vector unsigned __int128 vec_rlmi (vector unsigned __int128,

                                           vector unsigned __int128,                                           vector unsigned __int128);

vector signed __int128 vec_rlmi (vector signed __int128,

                                         vector signed __int128,                                         vector unsigned __int128);

Returns the result of rotating the first input and inserting it under maskinto the second input. The first bit in the mask, the last bit in the mask areobtained from the two 7-bit fields bits [108:115] and bits [117:123]respectively of the second input. The shift is obtained from the third inputin the 7-bit field [125:131] where all bits counted from zero at the left.

vector unsigned __int128 vec_rlnm (vector unsigned __int128,

                                           vector unsigned __int128,                                           vector unsigned __int128);

vector signed __int128 vec_rlnm (vector signed __int128,

                                         vector unsigned __int128,                                         vector unsigned __int128);

Returns the result of rotating the first input and ANDing it with a mask. Thefirst bit in the mask and the last bit in the mask are obtained from the two7-bit fields bits [117:123] and bits [125:131] respectively of the secondinput. The shift is obtained from the third input in the 7-bit field bits[125:131] where all bits counted from zero at the left.

vector unsigned __int128 vec_sl(vector unsigned __int128A, vector unsigned __int128B);

vector signed __int128 vec_sl(vector signed __int128A, vector unsigned __int128B);

Result value: Each element ofR is obtained by shifting the corresponding element ofA left by the number of bits specified by the corresponding element ofB.

vector unsigned __int128 vec_sr(vector unsigned __int128A, vector unsigned __int128B);

vector signed __int128 vec_sr(vector signed __int128A, vector unsigned __int128B);

Result value: Each element ofR is obtained by shifting the corresponding element ofA right by the number of bits specified by the corresponding element ofB.

vector unsigned __int128 vec_sra(vector unsigned __int128A, vector unsigned __int128B);

vector signed __int128 vec_sra(vector signed __int128A, vector unsigned __int128B);

Result value: Each element ofR is obtained by arithmetic shifting the correspondingelement ofA right by the number of bits specified by the corresponding element ofB.

vector unsigned __int128 vec_mule (vector unsigned long long,

                                           vector unsigned long long);

vector signed __int128 vec_mule (vector signed long long,

                                         vector signed long long);

Returns a vector containing a 128-bit integer result of multiplying the evendoubleword elements of the two inputs.

vector unsigned __int128 vec_mulo (vector unsigned long long,

                                           vector unsigned long long);

vector signed __int128 vec_mulo (vector signed long long,

                                         vector signed long long);

Returns a vector containing a 128-bit integer result of multiplying the odddoubleword elements of the two inputs.

vector unsigned __int128 vec_div (vector unsigned __int128,

                                          vector unsigned __int128);

vector signed __int128 vec_div (vector signed __int128,

                                        vector signed __int128);

Returns the result of dividing the first operand by the second operand. Anattempt to divide any value by zero or to divide the most negative signed128-bit integer by negative one results in an undefined value.

vector unsigned __int128 vec_dive (vector unsigned __int128,

                                           vector unsigned __int128);

vector signed __int128 vec_dive (vector signed __int128,

                                         vector signed __int128);

The result is produced by shifting the first input left by 128 bits anddividing by the second. If an attempt is made to divide by zero or the resultis larger than 128 bits, the result is undefined.

vector unsigned __int128 vec_mod (vector unsigned __int128,

                                          vector unsigned __int128);

vector signed __int128 vec_mod (vector signed __int128,

                                        vector signed __int128);

The result is the modulo result of dividing the first input by the secondinput.

The following builtins perform 128-bit vector comparisons. Thevec_all_xx,vec_any_xx, andvec_cmpxx, wherexx isone of the operationseq, ne, gt, lt, ge, le perform pairwisecomparisons between the elements at the same positions within their two vectorarguments. Thevec_all_xxfunction returns a non-zero value if and onlyif all pairwise comparisons are true. Thevec_any_xx function returnsa non-zero value if and only if at least one pairwise comparison is true. Thevec_cmpxxfunction returns a vector of the same type as its twoarguments, within which each element consists of all ones to denote thatspecified logical comparison of the corresponding elements was true.Otherwise, the element of the returned vector contains all zeros.

vector bool __int128 vec_cmpeq (vector signed __int128, vector signed __int128);vector bool __int128 vec_cmpeq (vector unsigned __int128, vector unsigned __int128);vector bool __int128 vec_cmpne (vector signed __int128, vector signed __int128);vector bool __int128 vec_cmpne (vector unsigned __int128, vector unsigned __int128);vector bool __int128 vec_cmpgt (vector signed __int128, vector signed __int128);vector bool __int128 vec_cmpgt (vector unsigned __int128, vector unsigned __int128);vector bool __int128 vec_cmplt (vector signed __int128, vector signed __int128);vector bool __int128 vec_cmplt (vector unsigned __int128, vector unsigned __int128);vector bool __int128 vec_cmpge (vector signed __int128, vector signed __int128);vector bool __int128 vec_cmpge (vector unsigned __int128, vector unsigned __int128);vector bool __int128 vec_cmple (vector signed __int128, vector signed __int128);vector bool __int128 vec_cmple (vector unsigned __int128, vector unsigned __int128);int vec_all_eq (vector signed __int128, vector signed __int128);int vec_all_eq (vector unsigned __int128, vector unsigned __int128);int vec_all_ne (vector signed __int128, vector signed __int128);int vec_all_ne (vector unsigned __int128, vector unsigned __int128);int vec_all_gt (vector signed __int128, vector signed __int128);int vec_all_gt (vector unsigned __int128, vector unsigned __int128);int vec_all_lt (vector signed __int128, vector signed __int128);int vec_all_lt (vector unsigned __int128, vector unsigned __int128);int vec_all_ge (vector signed __int128, vector signed __int128);int vec_all_ge (vector unsigned __int128, vector unsigned __int128);int vec_all_le (vector signed __int128, vector signed __int128);int vec_all_le (vector unsigned __int128, vector unsigned __int128);int vec_any_eq (vector signed __int128, vector signed __int128);int vec_any_eq (vector unsigned __int128, vector unsigned __int128);int vec_any_ne (vector signed __int128, vector signed __int128);int vec_any_ne (vector unsigned __int128, vector unsigned __int128);int vec_any_gt (vector signed __int128, vector signed __int128);int vec_any_gt (vector unsigned __int128, vector unsigned __int128);int vec_any_lt (vector signed __int128, vector signed __int128);int vec_any_lt (vector unsigned __int128, vector unsigned __int128);int vec_any_ge (vector signed __int128, vector signed __int128);int vec_any_ge (vector unsigned __int128, vector unsigned __int128);int vec_any_le (vector signed __int128, vector signed __int128);int vec_any_le (vector unsigned __int128, vector unsigned __int128);

The following instances are extension of the existing overloaded built-insvec_sld,vec_sldw,vec_slo,vec_sro,vec_srlthat are documented in the PVIPR.

vector signed __int128 vec_sld (vector signed __int128,

vector signed __int128, const unsigned int);

vector unsigned __int128 vec_sld (vector unsigned __int128,

vector unsigned __int128, const unsigned int);

vector signed __int128 vec_sldw (vector signed __int128,

vector signed __int128, const unsigned int);

vector unsigned __int128 vec_sldw (vector unsigned __int,

vector unsigned __int128, const unsigned int);

vector signed __int128 vec_slo (vector signed __int128,

vector signed char);

vector signed __int128 vec_slo (vector signed __int128,

vector unsigned char);

vector unsigned __int128 vec_slo (vector unsigned __int128,

vector signed char);

vector unsigned __int128 vec_slo (vector unsigned __int128,

vector unsigned char);

vector signed __int128 vec_sro (vector signed __int128,

vector signed char);

vector signed __int128 vec_sro (vector signed __int128,

vector unsigned char);

vector unsigned __int128 vec_sro (vector unsigned __int128,

vector signed char);

vector unsigned __int128 vec_sro (vector unsigned __int128,

vector unsigned char);

vector signed __int128 vec_srl (vector signed __int128,

vector unsigned char);

vector unsigned __int128 vec_srl (vector unsigned __int128,

vector unsigned char);