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-EB ¶-mebGenerate big-endian code.
-EL ¶-melGenerate little-endian code. This is the default for ‘mips*el-*-*’configurations.
-march=arch ¶Generate code that runs onarch, which can be the name of ageneric MIPS ISA, or the name of a particular processor.The ISA names are:‘mips1’, ‘mips2’, ‘mips3’, ‘mips4’,‘mips32’, ‘mips32r2’, ‘mips32r3’, ‘mips32r5’,‘mips32r6’, ‘mips64’, ‘mips64r2’, ‘mips64r3’,‘mips64r5’ and ‘mips64r6’.The processor names are:‘4kc’, ‘4km’, ‘4kp’, ‘4ksc’,‘4kec’, ‘4kem’, ‘4kep’, ‘4ksd’,‘5kc’, ‘5kf’,‘20kc’,‘24kc’, ‘24kf2_1’, ‘24kf1_1’,‘24kec’, ‘24kef2_1’, ‘24kef1_1’,‘34kc’, ‘34kf2_1’, ‘34kf1_1’, ‘34kn’,‘74kc’, ‘74kf2_1’, ‘74kf1_1’, ‘74kf3_2’,‘1004kc’, ‘1004kf2_1’, ‘1004kf1_1’,‘i6400’, ‘i6500’,‘interaptiv’,‘loongson2e’, ‘loongson2f’, ‘loongson3a’, ‘gs464’,‘gs464e’, ‘gs264e’,‘m4k’,‘m14k’, ‘m14kc’, ‘m14ke’, ‘m14kec’,‘m5100’, ‘m5101’,‘octeon’, ‘octeon+’, ‘octeon2’, ‘octeon3’,‘orion’,‘p5600’, ‘p6600’,‘r2000’, ‘r3000’, ‘r3900’, ‘r4000’, ‘r4400’,‘r4600’, ‘r4650’, ‘r4700’, ‘r5900’,‘r6000’, ‘r8000’,‘rm7000’, ‘rm9000’,‘r10000’, ‘r12000’, ‘r14000’, ‘r16000’,‘sb1’,‘sr71000’,‘vr4100’, ‘vr4111’, ‘vr4120’, ‘vr4130’, ‘vr4300’,‘vr5000’, ‘vr5400’, ‘vr5500’,‘xlr’ and ‘xlp’.‘allegrex’,The special value ‘from-abi’ selects themost compatible architecture for the selected ABI (that is,‘mips1’ for 32-bit ABIs and ‘mips3’ for 64-bit ABIs).
The native Linux/GNU toolchain also supports the value ‘native’,which selects the best architecture option for the host processor.-march=native has no effect if GCC does not recognizethe processor.
In processor names, a final ‘000’ can be abbreviated as ‘k’(for example,-march=r2k). Prefixes are optional, and‘vr’ may be written ‘r’.
Names of the form ‘nf2_1’ refer to processors withFPUs clocked at half the rate of the core, names of the form‘nf1_1’ refer to processors with FPUs clocked at the samerate as the core, and names of the form ‘nf3_2’ refer toprocessors with FPUs clocked a ratio of 3:2 with respect to the core.For compatibility reasons, ‘nf’ is accepted as a synonymfor ‘nf2_1’ while ‘nx’ and ‘bfx’ areaccepted as synonyms for ‘nf1_1’.
GCC defines two macros based on the value of this option. The firstis_MIPS_ARCH, which gives the name of target architecture, asa string. The second has the form_MIPS_ARCH_foo,wherefoo is the capitalized value of_MIPS_ARCH.For example,-march=r2000 sets_MIPS_ARCHto"r2000" and defines the macro_MIPS_ARCH_R2000.
Note that the_MIPS_ARCH macro uses the processor names givenabove. In other words, it has the full prefix and does notabbreviate ‘000’ as ‘k’. In the case of ‘from-abi’,the macro names the resolved architecture (either"mips1" or"mips3"). It names the default architecture when no-march option is given.
-mtune=arch ¶Optimize forarch. Among other things, this option controlsthe way instructions are scheduled, and the perceived cost of arithmeticoperations. The list ofarch values is the same as for-march.
When this option is not used, GCC optimizes for the processorspecified by-march. By using-march and-mtune together, it is possible to generate code thatruns on a family of processors, but optimize the code for oneparticular member of that family.
-mtune defines the macros_MIPS_TUNE and_MIPS_TUNE_foo, which work in the same way as the-march ones described above.
-mips1 ¶Equivalent to-march=mips1.
-mips2 ¶Equivalent to-march=mips2.
-mips3 ¶Equivalent to-march=mips3.
-mips4 ¶Equivalent to-march=mips4.
-mips32 ¶Equivalent to-march=mips32.
-mips32r3 ¶Equivalent to-march=mips32r3.
-mips32r5 ¶Equivalent to-march=mips32r5.
-mips32r6 ¶Equivalent to-march=mips32r6.
-mips64 ¶Equivalent to-march=mips64.
-mips64r2 ¶Equivalent to-march=mips64r2.
-mips64r3 ¶Equivalent to-march=mips64r3.
-mips64r5 ¶Equivalent to-march=mips64r5.
-mips64r6 ¶Equivalent to-march=mips64r6.
-mips16 ¶-mno-mips16Generate (do not generate) MIPS16 code. If GCC is targeting aMIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.
MIPS16 code generation can also be controlled on a per-function basisby means ofmips16 andnomips16 attributes.SeeDeclaring Attributes of Functions, for more information.
-mmips16e2 ¶-mno-mips16e2Use (do not use) the MIPS16e2 ASE. This option modifies the behaviorof the-mips16 option such that it targets the MIPS16e2 ASE.
-mflip-mips16 ¶-mflip-mips16Generate MIPS16 code on alternating functions. This option is providedfor regression testing of mixed MIPS16/non-MIPS16 code generation, and isnot intended for ordinary use in compiling user code.
-minterlink-compressed ¶-mno-interlink-compressedRequire (do not require) that code using the standard (uncompressed) MIPS ISAbe link-compatible with MIPS16 and microMIPS code, and vice versa.
For example, code using the standard ISA encoding cannot jump directlyto MIPS16 or microMIPS code; it must either use a call or an indirect jump.-minterlink-compressed therefore disables direct jumps unless GCCknows that the target of the jump is not compressed.
-minterlink-mips16 ¶-mno-interlink-mips16Aliases of-minterlink-compressed and-mno-interlink-compressed. These options predate the microMIPS ASEand are retained for backwards compatibility.
-mabi=32 ¶-mabi=o64-mabi=n32-mabi=64-mabi=eabiGenerate code for the given ABI.
Note that the EABI has a 32-bit and a 64-bit variant. GCC normallygenerates 64-bit code when you select a 64-bit architecture, but youcan use-mgp32 to get 32-bit code instead.
For information about the O64 ABI, seehttps://gcc.gnu.org/projects/mipso64-abi.html.
GCC supports a variant of the o32 ABI in which floating-point registersare 64 rather than 32 bits wide. You can select this combination with-mabi=32-mfp64. This ABI relies on themthc1andmfhc1 instructions and is therefore only supported forMIPS32R2, MIPS32R3 and MIPS32R5 processors.
The register assignments for arguments and return values remain thesame, but each scalar value is passed in a single 64-bit registerrather than a pair of 32-bit registers. For example, scalarfloating-point values are returned in ‘$f0’ only, not a‘$f0’/‘$f1’ pair. The set of call-saved registers alsoremains the same in that the even-numbered double-precision registersare saved.
Two additional variants of the o32 ABI are supported to enablea transition from 32-bit to 64-bit registers. These are FPXX(-mfpxx) and FP64A (-mfp64-mno-odd-spreg).The FPXX extension mandates that all code must execute correctlywhen run using 32-bit or 64-bit registers. The code can be interlinkedwith either FP32 or FP64, but not both.The FP64A extension is similar to the FP64 extension but forbids theuse of odd-numbered single-precision registers. This can be usedin conjunction with theFRE mode of FPUs in MIPS32R5processors and allows both FP32 and FP64A code to interlink andrun in the same process without changing FPU modes.
-mabicalls ¶-mno-abicallsGenerate (do not generate) code that is suitable for SVR4-styledynamic objects.-mabicalls is the default for SVR4-basedsystems.
-mshared ¶-mno-sharedGenerate (do not generate) code that is fully position-independent,and that can therefore be linked into shared libraries. This optiononly affects-mabicalls.
All-mabicalls code has traditionally been position-independent,regardless of options like-fPIC and-fpic. However,as an extension, the GNU toolchain allows executables to use absoluteaccesses for locally-binding symbols. It can also use shorter GPinitialization sequences and generate direct calls to locally-definedfunctions. This mode is selected by-mno-shared.
-mno-shared depends on binutils 2.16 or higher and generatesobjects that can only be linked by the GNU linker. However, the optiondoes not affect the ABI of the final executable; it only affects the ABIof relocatable objects. Using-mno-shared generally makesexecutables both smaller and quicker.
-mshared is the default.
-mplt ¶-mno-pltAssume (do not assume) that the static and dynamic linkerssupport PLTs and copy relocations. This option only affects-mno-shared -mabicalls. For the n64 ABI, this optionhas no effect without-msym32.
You can make-mplt the default by configuringGCC with--with-mips-plt. The default is-mno-plt otherwise.
-mxgot ¶-mno-xgotLift (do not lift) the usual restrictions on the size of the globaloffset table.
GCC normally uses a single instruction to load values from the GOT.While this is relatively efficient, it only works if the GOTis smaller than about 64k. Anything larger causes the linkerto report an error such as:
relocation truncated to fit: R_MIPS_GOT16 foobar
If this happens, you should recompile your code with-mxgot.This works with very large GOTs, although the code is alsoless efficient, since it takes three instructions to fetch thevalue of a global symbol.
Note that some linkers can create multiple GOTs. If you have such alinker, you should only need to use-mxgot when a single objectfile accesses more than 64k’s worth of GOT entries. Very few do.
These options have no effect unless GCC is generating positionindependent code.
-mgp32 ¶Assume that general-purpose registers are 32 bits wide.
-mgp64 ¶Assume that general-purpose registers are 64 bits wide.
-mfp32 ¶Assume that floating-point registers are 32 bits wide.
-mfp64 ¶Assume that floating-point registers are 64 bits wide.
-mfpxx ¶Do not assume the width of floating-point registers.
-mhard-float ¶Use floating-point coprocessor instructions.
-msoft-float ¶Do not use floating-point coprocessor instructions. Implementfloating-point calculations using library calls instead.
-mno-float ¶Equivalent to-msoft-float, but additionally asserts that theprogram being compiled does not perform any floating-point operations.This option is presently supported only by some bare-metal MIPSconfigurations, where it may select a special set of librariesthat lack all floating-point support (including, for example, thefloating-pointprintf formats).If code compiled with-mno-float accidentally containsfloating-point operations, it is likely to suffer a link-timeor run-time failure.
-msingle-float ¶Assume that the floating-point coprocessor only supports single-precisionoperations.
-mdouble-float ¶Assume that the floating-point coprocessor supports double-precisionoperations. This is the default.
-modd-spreg ¶-mno-odd-spregEnable the use of odd-numbered single-precision floating-point registersfor the o32 ABI. This is the default for processors that are known tosupport these registers. When using the o32 FPXX ABI,-mno-odd-spregis set by default.
-mabs=2008 ¶-mabs=legacyThese options control the treatment of the special not-a-number (NaN)IEEE 754 floating-point data with theabs.fmt andneg.fmt machine instructions.
By default or when-mabs=legacy is used the legacytreatment is selected. In this case these instructions are consideredarithmetic and avoided where correct operation is required and theinput operand might be a NaN. A longer sequence of instructions thatmanipulate the sign bit of floating-point datum manually is usedinstead unless the-ffinite-math-only option has also beenspecified.
The-mabs=2008 option selects the IEEE 754-2008 treatment. Inthis case these instructions are considered non-arithmetic and thereforeoperating correctly in all cases, including in particular where theinput operand is a NaN. These instructions are therefore always usedfor the respective operations.
-mnan=2008 ¶-mnan=legacyThese options control the encoding of the special not-a-number (NaN)IEEE 754 floating-point data.
The-mnan=legacy option selects the legacy encoding. In thiscase quiet NaNs (qNaNs) are denoted by the first bit of their trailingsignificand field being 0, whereas signaling NaNs (sNaNs) are denotedby the first bit of their trailing significand field being 1.
The-mnan=2008 option selects the IEEE 754-2008 encoding. Inthis case qNaNs are denoted by the first bit of their trailingsignificand field being 1, whereas sNaNs are denoted by the first bit oftheir trailing significand field being 0.
The default is-mnan=legacy unless GCC has been configured with--with-nan=2008.
-mllsc ¶-mno-llscUse (do not use) ‘ll’, ‘sc’, and ‘sync’ instructions toimplement atomic memory built-in functions. When neither option isspecified, GCC uses the instructions if the target architecturesupports them.
-mllsc is useful if the runtime environment can emulate theinstructions and-mno-llsc can be useful when compiling fornonstandard ISAs. You can make either option the default byconfiguring GCC with--with-llsc and--without-llscrespectively.--with-llsc is the default for someconfigurations; see the installation documentation for details.
-mdsp ¶-mno-dspUse (do not use) revision 1 of the MIPS DSP ASE.SeeMIPS DSP Built-in Functions. This option defines thepreprocessor macro__mips_dsp. It also defines__mips_dsp_rev to 1.
-mdspr2 ¶-mno-dspr2Use (do not use) revision 2 of the MIPS DSP ASE.SeeMIPS DSP Built-in Functions. This option defines thepreprocessor macros__mips_dsp and__mips_dspr2.It also defines__mips_dsp_rev to 2.
-msmartmips ¶-mno-smartmipsUse (do not use) the MIPS SmartMIPS ASE.
-mpaired-single ¶-mno-paired-singleUse (do not use) paired-single floating-point instructions.SeeMIPS Paired-Single Support. This option requireshardware floating-point support to be enabled.
-mdmx ¶-mno-mdmxUse (do not use) MIPS Digital Media Extension instructions.This option can only be used when generating 64-bit code and requireshardware floating-point support to be enabled.
-mips3d ¶-mno-mips3dUse (do not use) the MIPS-3D ASE. SeeMIPS-3D Built-in Functions.The option-mips3d implies-mpaired-single.
-mmicromips ¶-mno-micromipsGenerate (do not generate) microMIPS code.
MicroMIPS code generation can also be controlled on a per-function basisby means ofmicromips andnomicromips attributes.SeeDeclaring Attributes of Functions, for more information.
-mmt ¶-mno-mtUse (do not use) MT Multithreading instructions.
-mmcu ¶-mno-mcuUse (do not use) the MIPS MCU ASE instructions.
-meva ¶-mno-evaUse (do not use) the MIPS Enhanced Virtual Addressing instructions.
-mvirt ¶-mno-virtUse (do not use) the MIPS Virtualization (VZ) instructions.
-mxpa ¶-mno-xpaUse (do not use) the MIPS eXtended Physical Address (XPA) instructions.
-mcrc ¶-mno-crcUse (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions.
-mginv ¶-mno-ginvUse (do not use) the MIPS Global INValidate (GINV) instructions.
-mmsa ¶-mno-msaUse (do not use) the MIPS MSA extension instructions.
-mloongson-mmi ¶-mno-loongson-mmiUse (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI).
-mloongson-ext ¶-mno-loongson-extUse (do not use) the MIPS Loongson EXTensions (EXT) instructions.
-mloongson-ext2 ¶-mno-loongson-ext2Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions.
-mlong64 ¶Forcelong types to be 64 bits wide. See-mlong32 foran explanation of the default and the way that the pointer size isdetermined.
-mlong32 ¶Forcelong,int, and pointer types to be 32 bits wide.
The default size ofints,longs and pointers depends onthe ABI. All the supported ABIs use 32-bitints. The n64 ABIuses 64-bitlongs, as does the 64-bit EABI; the others use32-bitlongs. Pointers are the same size aslongs,or the same size as integer registers, whichever is smaller.
-msym32 ¶-mno-sym32Assume (do not assume) that all symbols have 32-bit values, regardlessof the selected ABI. This option is useful in combination with-mabi=64 and-mno-abicalls because it allows GCCto generate shorter and faster references to symbolic addresses.
-Gnum ¶Put definitions of externally-visible data in a small data sectionif that data is no bigger thannum bytes. GCC can then generatemore efficient accesses to the data; see-mgpopt for details.
The default-G option depends on the configuration.
-mlocal-sdata ¶-mno-local-sdataExtend (do not extend) the-G behavior to local data too,such as to static variables in C.-mlocal-sdata is thedefault for all configurations.
If the linker complains that an application is using too much small data,you might want to try rebuilding the less performance-critical parts with-mno-local-sdata. You might also want to build largelibraries with-mno-local-sdata, so that the libraries leavemore room for the main program.
-mextern-sdata ¶-mno-extern-sdataAssume (do not assume) that externally-defined data is ina small data section if the size of that data is within the-G limit.-mextern-sdata is the default for all configurations.
If you compile a moduleMod with-mextern-sdata-Gnum-mgpopt, andMod references a variableVarthat is no bigger thannum bytes, you must make sure thatVaris placed in a small data section. IfVar is defined by anothermodule, you must either compile that module with a high-enough-G setting or attach asection attribute toVar’sdefinition. IfVar is common, you must link the applicationwith a high-enough-G setting.
The easiest way of satisfying these restrictions is to compileand link every module with the same-G option. However,you may wish to build a library that supports several differentsmall data limits. You can do this by compiling the library withthe highest supported-G setting and additionally using-mno-extern-sdata to stop the library from making assumptionsabout externally-defined data.
-mgpopt ¶-mno-gpoptUse (do not use) GP-relative accesses for symbols that are known to bein a small data section; see-G,-mlocal-sdata and-mextern-sdata.-mgpopt is the default for allconfigurations.
-mno-gpopt is useful for cases where the$gp registermight not hold the value of_gp. For example, if the code ispart of a library that might be used in a boot monitor, programs thatcall boot monitor routines pass an unknown value in$gp.(In such situations, the boot monitor itself is usually compiledwith-G0.)
-mno-gpopt implies-mno-local-sdata and-mno-extern-sdata.
-membedded-data ¶-mno-embedded-dataAllocate variables to the read-only data section first if possible, thennext in the small data section if possible, otherwise in data. This givesslightly slower code than the default, but reduces the amount of RAM requiredwhen executing, and thus may be preferred for some embedded systems.
-muninit-const-in-rodata ¶-mno-uninit-const-in-rodataPut uninitializedconst variables in the read-only data section.This option is only meaningful in conjunction with-membedded-data.
-mcode-readable=setting ¶Specify whether GCC may generate code that reads from executable sections.There are three possible settings:
-mcode-readable=yesInstructions may freely access executable sections. This is thedefault setting.
-mcode-readable=pcrelMIPS16 PC-relative load instructions can access executable sections,but other instructions must not do so. This option is useful on 4KScand 4KSd processors when the code TLBs have the Read Inhibit bit set.It is also useful on processors that can be configured to have a dualinstruction/data SRAM interface and that, like the M4K, automaticallyredirect PC-relative loads to the instruction RAM.
-mcode-readable=noInstructions must not access executable sections. This option can beuseful on targets that are configured to have a dual instruction/dataSRAM interface but that (unlike the M4K) do not automatically redirectPC-relative loads to the instruction RAM.
On SDE targets,-mcode-data-in-code is available as atraditional alias for-mcode-readable=no, and-mcode-xonlyfor-mcode-readable=pcrel.
-msplit-addresses ¶-mno-split-addressesEnable (disable) use of the%hi() and%lo() assemblerrelocation operators. This option has been superseded by-mexplicit-relocs but is retained for backwards compatibility.
-mexplicit-relocs=none ¶-mexplicit-relocs=base-mexplicit-relocs=pcrel-mexplicit-relocs-mno-explicit-relocsThese options control whether explicit relocs (such as%gp_rel) are used.The default value depends on the version of GAS when GCC itself was built.
Thebase explicit-relocs support was introduced into GAS in 2001.Thepcrel explicit-relocs support was introduced into GAS in 2014,which supports%pcrel_hi and%pcrel_lo.
-mcheck-zero-division ¶-mno-check-zero-divisionTrap (do not trap) on integer division by zero.
The default is-mcheck-zero-division.
-mdivide-traps ¶-mdivide-breaksMIPS systems check for division by zero by generating either aconditional trap or a break instruction. Using traps results insmaller code, but is only supported on MIPS II and later. Also, someversions of the Linux kernel have a bug that prevents trap fromgenerating the proper signal (SIGFPE). Use-mdivide-traps toallow conditional traps on architectures that support them and-mdivide-breaks to force the use of breaks.
The default is usually-mdivide-traps, but this can beoverridden at configure time using--with-divide=breaks.Divide-by-zero checks can be completely disabled using-mno-check-zero-division.
-mload-store-pairs ¶-mno-load-store-pairsEnable (disable) an optimization that pairs consecutive load or storeinstructions to enable load/store bonding. This option is enabled bydefault but only takes effect when the selected architecture is knownto support bonding.
-mstrict-align ¶-mno-strict-align-munaligned-access-mno-unaligned-accessDisable (enable) direct unaligned access for MIPS Release 6.MIPSr6 requires load/store unaligned-access support, either by hardware orby trapping and emulation. In the latter case-mstrict-alignmay be needed by the operating system kernel. Theoptions-munaligned-access and-mno-unaligned-accessare obsolete, and only provided for backward compatibility.
-mmemcpy ¶-mno-memcpyForce (do not force) the use ofmemcpy for non-trivial blockmoves. The default is-mno-memcpy, which allows GCC to inlinemost constant-sized copies.
-mlong-calls ¶-mno-long-callsDisable (do not disable) use of thejal instruction. Callingfunctions usingjal is more efficient but requires the callerand callee to be in the same 256 megabyte segment.
This option has no effect on abicalls code. The default is-mno-long-calls.
-mmad ¶-mno-madEnable (disable) use of themad,madu andmulinstructions, as provided by the R4650 ISA.
-mimadd ¶-mno-imaddEnable (disable) use of themadd andmsub integerinstructions. The default is-mimadd on architecturesthat supportmadd andmsub except for the 74karchitecture where it was found to generate slower code.
-mfused-madd ¶-mno-fused-maddEnable (disable) use of the floating-point multiply-accumulateinstructions, when they are available. The default is-mfused-madd.
On the R8000 CPU when multiply-accumulate instructions are used,the intermediate product is calculated to infinite precisionand is not subject to the FCSR Flush to Zero bit. This may beundesirable in some circumstances. On other processors the resultis numerically identical to the equivalent computation usingseparate multiply, add, subtract and negate instructions.
-nocpp ¶Tell the MIPS assembler to not run its preprocessor over userassembler files (with a ‘.s’ suffix) when assembling them.
-mfix-24k ¶-mno-fix-24kWork around the 24K E48 (lost data on stores during refill) errata.The workarounds are implemented by the assembler rather than by GCC.
-mfix-r4000 ¶-mno-fix-r4000Work around certain R4000 CPU errata:
-mfix-r4400 ¶-mno-fix-r4400Work around certain R4400 CPU errata:
-mfix-r10000 ¶-mno-fix-r10000Work around certain R10000 errata:
ll/sc sequences may not behave atomically on revisionsprior to 3.0. They may deadlock on revisions 2.6 and earlier.This option can only be used if the target architecture supportsbranch-likely instructions.-mfix-r10000 is the default when-march=r10000 is used;-mno-fix-r10000 is the defaultotherwise.
-mfix-r5900 ¶-mno-fix-r5900Do not attempt to schedule the preceding instruction into the delay slotof a branch instruction placed at the end of a short loop of sixinstructions or fewer and always schedule anop instruction thereinstead. The short loop bug under certain conditions causes loops toexecute only once or twice, due to a hardware bug in the R5900 chip. Theworkaround is implemented by the assembler rather than by GCC.
-mfix-rm7000 ¶-mno-fix-rm7000Work around the RM7000dmult/dmultu errata. Theworkarounds are implemented by the assembler rather than by GCC.
-mfix-vr4120 ¶-mno-fix-vr4120Work around certain VR4120 errata:
dmultu does not always produce the correct result.div andddiv do not always produce the correct result if oneof the operands is negative.The workarounds for the division errata rely on special functions inlibgcc.a. At present, these functions are only provided bythemips64vr*-elf configurations.
Other VR4120 errata require a NOP to be inserted between certain pairs ofinstructions. These errata are handled by the assembler, not by GCC itself.
-mfix-vr4130 ¶-mno-fix-vr4130Work around the VR4130mflo/mfhi errata. Theworkarounds are implemented by the assembler rather than by GCC,although GCC avoids usingmflo andmfhi if theVR4130macc,macchi,dmacc anddmacchiinstructions are available instead.
-mfix-sb1 ¶-mno-fix-sb1Work around certain SB-1 CPU core errata.(This flag currently works around the SB-1 revision 2“F1” and “F2” floating-point errata.)
-mfix4300 ¶-mno-fix4300Work around a bug in early VR4300 silicon that causes multiplies withcertain operands to corrupt immediately following multiplies.
-mr10k-cache-barrier=setting ¶Specify whether GCC should insert cache barriers to avoid theside effects of speculation on R10K processors.
In common with many processors, the R10K tries to predict the outcomeof a conditional branch and speculatively executes instructions fromthe “taken” branch. It later aborts these instructions if thepredicted outcome is wrong. However, on the R10K, even abortedinstructions can have side effects.
This problem only affects kernel stores and, depending on the system,kernel loads. As an example, a speculatively-executed store may loadthe target memory into cache and mark the cache line as dirty, even ifthe store itself is later aborted. If a DMA operation writes to thesame area of memory before the “dirty” line is flushed, the cacheddata overwrites the DMA-ed data. See the R10K processor manualfor a full description, including other potential problems.
One workaround is to insert cache barrier instructions before every memoryaccess that might be speculatively executed and that might have sideeffects even if aborted.-mr10k-cache-barrier=settingcontrols GCC’s implementation of this workaround. It assumes thataborted accesses to any byte in the following regions does not haveside effects:
It is the kernel’s responsibility to ensure that speculativeaccesses to these regions are indeed safe.
If the input program contains a function declaration such as:
void foo (void);
then the implementation offoo must allowj foo andjal foo to be executed speculatively. GCC honors thisrestriction for functions it compiles itself. It expects non-GCCfunctions (such as hand-written assembly code) to do the same.
The option has three forms:
-mr10k-cache-barrier=load-storeInsert a cache barrier before a load or store that might bespeculatively executed and that might have side effects evenif aborted.
-mr10k-cache-barrier=storeInsert a cache barrier before a store that might be speculativelyexecuted and that might have side effects even if aborted.
-mr10k-cache-barrier=noneDisable the insertion of cache barriers. This is the default setting.
-mflush-func=func ¶-mno-flush-funcSpecifies the function to call to flush the I and D caches, or to notcall any such function. If called, the function must take the samearguments as the common_flush_func, that is, the address of thememory range for which the cache is being flushed, the size of thememory range, and the number 3 (to flush both caches). The defaultdepends on the target GCC was configured for, but commonly is either_flush_func or__cpu_flush.
-mbranch-cost=num ¶Set the cost of branches to roughlynum “simple” instructions.This cost is only a heuristic and is not guaranteed to produceconsistent results across releases. A zero cost redundantly selectsthe default, which is based on the-mtune setting.
-mbranch-likely ¶-mno-branch-likelyEnable or disable use of Branch Likely instructions, regardless of thedefault for the selected architecture. By default, Branch Likelyinstructions may be generated if they are supported by the selectedarchitecture. An exception is for the MIPS32 and MIPS64 architecturesand processors that implement those architectures; for those, BranchLikely instructions are not be generated by default because the MIPS32and MIPS64 architectures specifically deprecate their use.
-mcompact-branches=never ¶-mcompact-branches=optimal-mcompact-branches=alwaysThese options control which form of branches are generated. Thedefault is-mcompact-branches=optimal.
The-mcompact-branches=never option ensures that compact branchinstructions are never generated.
The-mcompact-branches=always option ensures that a compactbranch instruction is generated if available for MIPS Release 6 onwards.If a compact branch instruction is not available (or pre-R6),a delay slot form of the branch is used instead.
If it is used for MIPS16/microMIPS targets, it is just ignored now.The behavior for MIPS16/microMIPS may change in future,since they do have some compact branch instructions.
The-mcompact-branches=optimal option causes a delay slotbranch to be used if one is available in the current ISA and the delayslot is successfully filled. If the delay slot is not filled, a compactbranch is chosen if one is available.
-mfp-exceptions ¶-mno-fp-exceptionsSpecifies whether FP exceptions are enabled. This affects howFP instructions are scheduled for some processors.The default is that FP exceptions areenabled.
For instance, on the SB-1, if FP exceptions are disabled, and we are emitting64-bit code, then we can use both FP pipes. Otherwise, we can only use oneFP pipe.
-mvr4130-align ¶-mno-vr4130-alignThe VR4130 pipeline is two-way superscalar, but can only issue twoinstructions together if the first one is 8-byte aligned. When thisoption is enabled, GCC aligns pairs of instructions that itthinks should execute in parallel.
This option only has an effect when optimizing for the VR4130.It normally makes code faster, but at the expense of making it bigger.It is enabled by default at optimization level-O3.
-msynci ¶-mno-synciEnable (disable) generation ofsynci instructions onarchitectures that support it. Thesynci instructions (ifenabled) are generated when__builtin___clear_cache iscompiled.
This option defaults to-mno-synci, but the default can beoverridden by configuring GCC with--with-synci.
When compiling code for single processor systems, it is generally safeto usesynci. However, on many multi-core (SMP) systems, itdoes not invalidate the instruction caches on all cores and may leadto undefined behavior.
-mrelax-pic-calls ¶-mno-relax-pic-callsTry to turn PIC calls that are normally dispatched via register$25 into direct calls. This is only possible if the linker canresolve the destination at link time and if the destination is withinrange for a direct call.
-mrelax-pic-calls is the default if GCC was configured to usean assembler and a linker that support the.reloc assemblydirective and-mexplicit-relocs is in effect. With-mno-explicit-relocs, this optimization can be performed by theassembler and the linker alone without help from the compiler.
-mmcount-ra-address ¶-mno-mcount-ra-addressEmit (do not emit) code that allows_mcount to modify thecalling function’s return address. When enabled, this option extendsthe usual_mcount interface with a newra-addressparameter, which has typeintptr_t * and is passed in register$12._mcount can then modify the return address bydoing both of the following:
$31.*ra-address,ifra-address is nonnull.The default is-mno-mcount-ra-address.
-mframe-header-opt ¶-mno-frame-header-optEnable (disable) frame header optimization in the o32 ABI. When using theo32 ABI, calling functions allocates 16 bytes on the stack for the calledfunction to write out register arguments. When enabled, this optimizationsuppresses the allocation of the frame header if it can be determined thatit is unused.
This optimization is off by default at all optimization levels.
-mlxc1-sxc1 ¶-mno-lxc1-sxc1When applicable, enable (disable) the generation oflwxc1,swxc1,ldxc1,sdxc1 instructions. Enabled by default.
-mmadd4 ¶-mno-madd4When applicable, enable (disable) the generation of 4-operandmadd.s,madd.d and related instructions. Enabled by default.
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