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These ‘-m’ options are defined for the DEC Alpha implementations:
-mno-soft-float ¶-msoft-floatUse (do not use) the hardware floating-point instructions forfloating-point operations. When-msoft-float is specified,functions inlibgcc.a are used to perform floating-pointoperations. Unless they are replaced by routines that emulate thefloating-point operations, or compiled in such a way as to call suchemulations routines, these routines issue floating-pointoperations. If you are compiling for an Alpha without floating-pointoperations, you must ensure that the library is built so as not to callthem.
Note that Alpha implementations without floating-point operations arerequired to have floating-point registers.
-mfp-regs ¶-mno-fp-regsGenerate code that uses (does not use) the floating-point register set.-mno-fp-regs implies-msoft-float. If the floating-pointregister set is not used, floating-point operands are passed in integerregisters as if they were integers and floating-point results are passedin$0 instead of$f0. This is a non-standard calling sequence,so any function with a floating-point argument or return value called by codecompiled with-mno-fp-regs must also be compiled with thatoption.
A typical use of this option is building a kernel that does not use,and hence need not save and restore, any floating-point registers.
-mieee ¶The Alpha architecture implements floating-point hardware optimized formaximum performance. It is mostly compliant with the IEEE floating-pointstandard. However, for full compliance, software assistance isrequired. This option generates code fully IEEE-compliant codeexcept that theinexact-flag is not maintained (see below).If this option is turned on, the preprocessor macro_IEEE_FP isdefined during compilation. The resulting code is less efficient but isable to correctly support denormalized numbers and exceptional IEEEvalues such as not-a-number and plus/minus infinity. Other Alphacompilers call this option-ieee_with_no_inexact.
-mieee-with-inexact ¶This is like-mieee except the generated code also maintainsthe IEEEinexact-flag. Turning on this option causes thegenerated code to implement fully-compliant IEEE math. In addition to_IEEE_FP,_IEEE_FP_EXACT is defined as a preprocessormacro. On some Alpha implementations the resulting code may executesignificantly slower than the code generated by default. Since there isvery little code that depends on theinexact-flag, you shouldnormally not specify this option. Other Alpha compilers call thisoption-ieee_with_inexact.
-mfp-trap-mode=trap-mode ¶This option controls what floating-point related traps are enabled.Other Alpha compilers call this option-fptmtrap-mode.The trap mode can be set to one of four values:
This is the default (normal) setting. The only traps that are enabledare the ones that cannot be disabled in software (e.g., division by zerotrap).
In addition to the traps enabled by ‘n’, underflow traps are enabledas well.
Like ‘u’, but the instructions are marked to be safe for softwarecompletion (see Alpha architecture manual for details).
Like ‘su’, but inexact traps are enabled as well.
-mfp-rounding-mode=rounding-mode ¶Selects the IEEE rounding mode. Other Alpha compilers call this option-fprmrounding-mode. Therounding-mode can be oneof:
Normal IEEE rounding mode. Floating-point numbers are rounded towardsthe nearest machine number or towards the even machine number in caseof a tie.
Round towards minus infinity.
Chopped rounding mode. Floating-point numbers are rounded towards zero.
Dynamic rounding mode. A field in the floating-point control register(fpcr, see Alpha architecture reference manual) controls therounding mode in effect. The C library initializes this register forrounding towards plus infinity. Thus, unless your program modifies thefpcr, ‘d’ corresponds to round towards plus infinity.
-mtrap-precision=trap-precision ¶In the Alpha architecture, floating-point traps are imprecise. Thismeans without software assistance it is impossible to recover from afloating trap and program execution normally needs to be terminated.GCC can generate code that can assist operating system trap handlersin determining the exact location that caused a floating-point trap.Depending on the requirements of an application, different levels ofprecisions can be selected:
Program precision. This option is the default and means a trap handlercan only identify which program caused a floating-point exception.
Function precision. The trap handler can determine the function thatcaused a floating-point exception.
Instruction precision. The trap handler can determine the exactinstruction that caused a floating-point exception.
Other Alpha compilers provide the equivalent options called-scope_safe and-resumption_safe.
-mieee-conformant ¶This option marks the generated code as IEEE conformant. You must notuse this option unless you also specify-mtrap-precision=i and either-mfp-trap-mode=su or-mfp-trap-mode=sui. Its only effectis to emit the line ‘.eflag 48’ in the function prologue of thegenerated assembly file.
-mbuild-constants ¶Normally GCC examines a 32- or 64-bit integer constant tosee if it can construct it from smaller constants in two or threeinstructions. If it cannot, it outputs the constant as a literal andgenerates code to load it from the data segment at run time.
Use this option to require GCC to constructall integer constantsusing code, even if it takes more instructions (the maximum is six).
You typically use this option to build a shared library dynamicloader. Itself a shared library, it must relocate itself in memorybefore it can find the variables and constants in its own data segment.
-mbwx ¶-mno-bwx-mcix-mno-cix-mfix-mno-fix-mmax-mno-maxIndicate whether GCC should generate code to use the optional BWX,CIX, FIX and MAX instruction sets. The default is to use the instructionsets supported by the CPU type specified via-mcpu= option or thatof the CPU on which GCC was built if none is specified.
-msafe-bwa ¶-mno-safe-bwaIndicate whether in the absence of the optional BWX instruction setGCC should generate multi-thread and async-signal safe code for byteand aligned word memory accesses.
-msafe-partial ¶-mno-safe-partialIndicate whether GCC should generate multi-thread and async-signalsafe code for partial memory accesses, including piecemeal accessesto unaligned data as well as block accesses to leading and trailingparts of aggregate types or other objects in memory that do notrespectively start and end on an aligned 64-bit data boundary.
-mfloat-vax ¶-mfloat-ieeeGenerate code that uses (does not use) VAX F and G floating-pointarithmetic instead of IEEE single and double precision.
-mexplicit-relocs ¶-mno-explicit-relocsOlder Alpha assemblers provided no way to generate symbol relocationsexcept via assembler macros. Use of these macros does not allowoptimal instruction scheduling. GNU Binutils as of version 2.12supports a new syntax that allows the compiler to explicitly markwhich relocations should apply to which instructions. This optionis mostly useful for debugging, as GCC detects the capabilities ofthe assembler when it is built and sets the default accordingly.
-msmall-data ¶-mlarge-dataWhen-mexplicit-relocs is in effect, static data isaccessed viagp-relative relocations. When-msmall-datais used, objects 8 bytes long or smaller are placed in asmall data area(the.sdata and.sbss sections) and are accessed via16-bit relocations off of the$gp register. This limits thesize of the small data area to 64KB, but allows the variables to bedirectly accessed via a single instruction.
The default is-mlarge-data. With this option the data areais limited to just below 2GB. Programs that require more than 2GB ofdata must usemalloc ormmap to allocate the data in theheap instead of in the program’s data segment.
When generating code for shared libraries,-fpic implies-msmall-data and-fPIC implies-mlarge-data.
-msmall-text ¶-mlarge-textWhen-msmall-text is used, the compiler assumes that thecode of the entire program (or shared library) fits in 4MB, and isthus reachable with a branch instruction. When-msmall-datais used, the compiler can assume that all local symbols share thesame$gp value, and thus reduce the number of instructionsrequired for a function call from 4 to 1.
The default is-mlarge-text.
-mcpu=cpu_type ¶Set the instruction set and instruction scheduling parameters formachine typecpu_type. You can specify either the ‘EV’style name or the corresponding chip number. GCC supports schedulingparameters for the EV4, EV5 and EV6 family of processors andchooses the default values for the instruction set from the processoryou specify. If you do not specify a processor type, GCC defaultsto the processor on which the compiler was built.
Supported values forcpu_type are
Schedules as an EV4 and has no instruction set extensions.
Schedules as an EV5 and has no instruction set extensions.
Schedules as an EV5 and supports the BWX extension.
Schedules as an EV5 and supports the BWX and MAX extensions.
Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
Native toolchains also support the value ‘native’,which selects the best architecture option for the host processor.-mcpu=native has no effect if GCC does not recognizethe processor.
-mtune=cpu_type ¶Set only the instruction scheduling parameters for machine typecpu_type. The instruction set is not changed.
Native toolchains also support the value ‘native’,which selects the best architecture option for the host processor.-mtune=native has no effect if GCC does not recognizethe processor.
-mmemory-latency=time ¶Sets the latency the scheduler should assume for typical memoryreferences as seen by the application. This number is highlydependent on the memory access patterns used by the applicationand the size of the external cache on the machine.
Valid options fortime are
A decimal number representing clock cycles.
The compiler contains estimates of the number of clock cycles for“typical” EV4 & EV5 hardware for the Level 1, 2 & 3 caches(also called Dcache, Scache, and Bcache), as well as to main memory.Note that L3 is only valid for EV5.
-mtls-kernel ¶Emitrdval instead ofrduniq for thread pointer.
-mtls-size=bitsize ¶Specify bit size of immediate TLS offsets. Valid values forbitsizeare 16, 32, and 64; it defaults to 32.
-mlong-double-128 ¶-mlong-double-64Specify the size of thelong double type. Note that-mlong-double-128 is incompatible with VAX floating point.
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