Movatterモバイル変換

Next:Blackfin Options, Previous:ARM Options, Up:Machine-Dependent Options   [Contents][Index]

3.21.6.1 AVR Optimization Options ¶

The following options are pure optimization options.Options-mgas-isr-prologues,-mmain-is-OS_task,-mno-call-main and-mrelax from above are onlyalmost optimization options, since there are rare occasionswhere their different code generation matters.

-maccumulate-args ¶

Accumulate outgoing function arguments and acquire/release the neededstack space for outgoing function arguments once in functionprologue/epilogue. Without this option, outgoing arguments are pushedbefore calling a function and popped afterwards.See also the-fdefer-popoptimization option.

Popping the arguments after the function call can be expensive onAVR so that accumulating the stack space might lead to smallerexecutables because arguments need not be removed from thestack after such a function call.

This option can lead to reduced code size for functions that performseveral calls to functions that get their arguments on the stack likecalls to printf-like functions.

-mbranch-cost=cost ¶

Set the branch costs for conditional branch instructions tocost. Reasonable values forcost are small, non-negativeintegers. The default branch cost is 0.

-mcall-prologues ¶

Functions prologues/epilogues are expanded as calls to appropriatesubroutines. Code size is smaller.

-mfuse-add ¶

-mno-fuse-add

-mfuse-add=level

Optimize indirect memory accesses on reduced Tiny devices.The default useslevel=1 for optimizations-Ogand-O1, andlevel=2 for higher optimizations.Valid values forlevel are0,1 and2.

-mfuse-move ¶

-mno-fuse-move

-mfuse-move=level

Run a post reload optimization pass that tries to fuse move instructionsand to split multi-byte instructions into 8-bit operations.The default useslevel=3 for optimization-O1,andlevel=23 for higher optimizations.Valid values forlevel are in the range0 …23which is a 3:2:2:2 mixed radix value. Each digit controls someaspect of the optimization.

-mfuse-move2 ¶

Run a post combine optimization pass that tries to fuse move instructions.

-mstrict-X ¶

Use address registerX in a way proposed by the hardware. This meansthatX is only used in indirect, post-increment orpre-decrement addressing.

Without this option, theX register may be used in the same wayasY orZ which then is emulated by additionalinstructions.For example, loading a value withX+const addressing with asmall non-negativeconst < 64 to a registerRn isperformed as

adiw r26, const   ; X += constldRn, X        ;Rn = *Xsbiw r26, const   ; X -= const

-msplit-bit-shift ¶

Split multi-byte shifts with a constant offset into a shift witha byte offset and a residual shift with a non-byte offset.This optimization is turned on per default for-O2 and higher,including-Os but excluding-Oz.Splitting of shifts with a constant offset that isa multiple of 8 is controlled by-mfuse-move.

-msplit-ldst ¶

Split multi-byte loads and stores into several byte loads and stores.This optimization is turned on per default for-O2 and higher.

-muse-nonzero-bits ¶

Enable optimizations that are only possible when some bits in aregister are always zero.This optimization is turned on per default for-O2 and higher.

3.21.6.2EIND and Devices with More Than 128 Ki Bytes of Flash ¶

Pointers in the implementation are 16 bits wide.The address of a function or label is represented as word address sothat indirect jumps and calls can target any code address in therange of 64 Ki words.

In order to facilitate indirect jump on devices with more than 128 Kibytes of program memory space, there is a special function register calledEIND that serves as most significant part of the target addresswhenEICALL orEIJMP instructions are used.

Indirect jumps and calls on these devices are handled as follows bythe compiler and are subject to some limitations:

• The compiler never setsEIND.
• The compiler usesEIND implicitly inEICALL/EIJMPinstructions or might readEIND directly in order to emulate anindirect call/jump by means of aRET instruction.
• The compiler assumes thatEIND never changes during the startupcode or during the application. In particular,EIND is notsaved/restored in function or interrupt service routineprologue/epilogue.
• For indirect calls to functions and computed goto, the linkergeneratesstubs. Stubs are jump pads sometimes also calledtrampolines. Thus, the indirect call/jump jumps to such a stub.The stub contains a direct jump to the desired address.
• Linker relaxation must be turned on so that the linker generatesthe stubs correctly in all situations. See the compiler option-mrelax and the linker option--relax.There are corner cases where the linker is supposed to generate stubsbut aborts without relaxation and without a helpful error message.
• The default linker script is arranged for code withEIND = 0.If code is supposed to work for a setup withEIND != 0, a customlinker script has to be used in order to place the sections whosename start with.trampolines into the segment whereEINDpoints to.
• The startup code from libgcc never setsEIND.Notice that startup code is a blend of code from libgcc and AVR-LibC.For the impact of AVR-LibC onEIND, see theAVR-LibC user manual.
• It is legitimate for user-specific startup code to set upEINDearly, for example by means of initialization code located insection.init3. Such code runs prior to general startup codethat initializes RAM and calls constructors, but after the bitof startup code from AVR-LibC that setsEIND to the segmentwhere the vector table is located.

  #include <avr/io.h>static void__attribute__((section(".init3"),naked,used,no_instrument_function))init3_set_eind (void){  __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t"                  "out %i0,r24" :: "n" (&EIND) : "r24","memory");}

  The__trampolines_start symbol is defined in the linker script.

• Stubs are generated automatically by the linker ifthe following two conditions are met:
  • The address of a label is taken by means of thegs modifier(short forgenerate stubs) like so:

    LDI r24, lo8(gs(func))LDI r25, hi8(gs(func))

  • The final location of that label is in a code segmentoutside the segment where the stubs are located.
• The compiler emits suchgs modifiers for code labels in thefollowing situations:
  • Taking address of a function or code label.
  • Computed goto.
  • If prologue-save function is used, see-mcall-prologuescommand-line option.
  • Switch/case dispatch tables. If you do not want such dispatchtables you can specify the-fno-jump-tables command-line option.
  • C and C++ constructors/destructors called during startup/shutdown.
  • If the tools hit ags() modifier explained above.
• Jumping to non-symbolic addresses like so isnot supported:

  int main (void){    /* Call function at word address 0x2 */    return ((int(*)(void)) 0x2)();}

  Instead, a stub has to be set up, i.e. the function has to be calledthrough a symbol (func_4 in the example):

  int main (void){    extern int func_4 (void);    /* Call function at byte address 0x4 */    return func_4();}

  and the application be linked with-Wl,--defsym,func_4=0x4.Alternatively,func_4 can be defined in the linker script.

3.21.6.3 Handling of theRAMPD,RAMPX,RAMPY andRAMPZ Special Function Registers ¶

Some AVR devices support memories larger than the 64 KiB rangethat can be accessed with 16-bit pointers. To access memory locationsoutside this 64 KiB range, the content of aRAMPregister is used as high part of the address:TheX,Y,Z address register is concatenatedwith theRAMPX,RAMPY,RAMPZ special functionregister, respectively, to get a wide address. Similarly,RAMPD is used together with direct addressing.

• The startup code initializes theRAMP special functionregisters with zero.
• If anamed address space other thangeneric or__flash is used, thenRAMPZ is setas needed before the operation.
• If the device supports RAM larger than 64 KiB and the compilerneeds to changeRAMPZ to accomplish an operation,RAMPZis reset to zero after the operation.
• If the device comes with a specificRAMP register, the ISRprologue/epilogue saves/restores that SFR and initializes it withzero in case the ISR code might (implicitly) use it.
• RAM larger than 64 KiB is not supported by GCC for AVR targets.If you use inline assembler to read from locations outside the16-bit address range and change one of theRAMP registers,you must reset it to zero after the access.

3.21.6.4 AVR Built-in Macros ¶

GCC defines several built-in macros so that the user code can testfor the presence or absence of features. Almost any of the followingbuilt-in macros are deduced from device capabilities and thustriggered by the-mmcu= command-line option.

For even more AVR-specific built-in macros seeAVR Named Address Spaces andAVR Built-in Functions.

__AVR_ARCH__

Build-in macro that resolves to a decimal number that identifies thearchitecture and depends on the-mmcu=mcu option.Possible values are:

2,25,3,31,35,4,5,51,6

formcu=avr2,avr25,avr3,avr31,avr35,avr4,avr5,avr51,avr6,

respectively and

100,102,103,104,105,106,107

formcu=avrtiny,avrxmega2,avrxmega3,avrxmega4,avrxmega5,avrxmega6,avrxmega7, respectively.Ifmcu specifies a device, this built-in macro is setaccordingly. For example, with-mmcu=atmega8 the macro isdefined to4.

__AVR_Device__

Setting-mmcu=device defines this built-in macro which reflectsthe device’s name. For example,-mmcu=atmega8 defines thebuilt-in macro__AVR_ATmega8__,-mmcu=attiny261a defines__AVR_ATtiny261A__, etc.

The built-in macros’ names followthe scheme__AVR_Device__ whereDevice isthe device name as from the AVR user manual. The difference betweenDevice in the built-in macro anddevice in-mmcu=device is that the latter is always lowercase.

Ifdevice is not a device but only a core architecture like‘avr51’, this macro is not defined.

__AVR_DEVICE_NAME__

Setting-mmcu=device defines this built-in macro tothe device’s name. For example, with-mmcu=atmega8 the macrois defined toatmega8.

Ifdevice is not a device but only a core architecture like‘avr51’, this macro is not defined.

__AVR_CVT__

The code is being compiled with option-mcvt to use acompact vector table.

__AVR_XMEGA__

The device / architecture belongs to the XMEGA family of devices.

__AVR_HAVE_ADIW__

The device has theADIW andSBIW instructions.

__AVR_HAVE_ELPM__

The device has theELPM instruction.

__AVR_HAVE_ELPMX__

The device has theELPM Rn,Z andELPMRn,Z+ instructions.

__AVR_HAVE_LPMX__

The device has theLPM Rn,Z andLPM Rn,Z+ instructions.

__AVR_HAVE_MOVW__

The device has theMOVW instruction to perform 16-bitregister-register moves.

__AVR_HAVE_MUL__

The device has a hardware multiplier.

__AVR_HAVE_JMP_CALL__

The device has theJMP andCALL instructions.This is the case for devices with more than 8 KiB of programmemory.

__AVR_HAVE_EIJMP_EICALL__

__AVR_3_BYTE_PC__

The device has theEIJMP andEICALL instructions.This is the case for devices with more than 128 KiB of program memory.This also means that the program counter(PC) is 3 bytes wide.

__AVR_2_BYTE_PC__

The program counter (PC) is 2 bytes wide. This is the case for deviceswith up to 128 KiB of program memory.

__AVR_HAVE_8BIT_SP__

__AVR_HAVE_16BIT_SP__

The stack pointer (SP) register is treated as 8-bit respectively16-bit register by the compiler.The definition of these macros is affected by-mtiny-stack.

__AVR_HAVE_SPH__

__AVR_SP8__

The device has the SPH (high part of stack pointer) special functionregister or has an 8-bit stack pointer, respectively.The definition of these macros is affected by-mmcu= andin the cases of-mmcu=avr2 and-mmcu=avr25 alsoby-msp8.

__AVR_HAVE_RAMPD__

__AVR_HAVE_RAMPX__

__AVR_HAVE_RAMPY__

__AVR_HAVE_RAMPZ__

The device has theRAMPD,RAMPX,RAMPY,RAMPZ special function register, respectively.

__NO_INTERRUPTS__

This macro reflects the-mno-interrupts command-line option.

__AVR_ERRATA_SKIP__

__AVR_ERRATA_SKIP_JMP_CALL__

Some AVR devices (AT90S8515, ATmega103) must not skip 32-bitinstructions because of a hardware erratum. Skip instructions areSBRS,SBRC,SBIS,SBIC andCPSE.The second macro is only defined if__AVR_HAVE_JMP_CALL__ is alsoset.

__AVR_ISA_RMW__

The device has Read-Modify-Write instructions (XCH, LAC, LAS and LAT).

__AVR_SFR_OFFSET__=offset

Instructions that can address I/O special function registers directlylikeIN,OUT,SBI, etc. may use a differentaddress as if addressed by an instruction to access RAM likeLDorSTS. This offset depends on the device architecture and hasto be subtracted from the RAM address in order to get therespective I/O address.

__AVR_SHORT_CALLS__

The-mshort-calls command line option is set.

__AVR_PM_BASE_ADDRESS__=addr

Some devices support reading from flash memory by means ofLD*instructions. The flash memory is seen in the data address spaceat an offset of__AVR_PM_BASE_ADDRESS__. If this macrois not defined, this feature is not available. If defined,the address space is linear and there is no need to put.rodata into RAM. This is handled by the default linkerdescription file, and is currently available foravrtiny andavrxmega3. Even more convenient,there is no need to use address spaces like__flash orfeatures like attributeprogmem andpgm_read_*.

__AVR_HAVE_FLMAP__

This macro is defined provided the following conditions are met:

• The device has theNVMCTRL_CTRLB.FLMAP bitfield.This applies to the AVR64* and AVR128* devices.
• It’s not known at assembler-time which emulation will be used.

This implies the compiler was configured with GNU Binutils that implementPR31124.

__AVR_RODATA_IN_RAM__

This macro is undefined when the code is compiled for a core architecture.

When the code is compiled for a device, the macro is defined to 1when the.rodata sections for read-only data is located in RAM;and defined to 0, otherwise.

__WITH_AVRLIBC__

The compiler is configured to be used together with AVR-LibC.See the--with-avrlibc configure option.

__HAVE_SIGNAL_N__

The compiler supports thesignal(num) andinterrupt(num)function attributeswith an argumentnum that specifies the number of theinterrupt service routine.

__HAVE_DOUBLE_MULTILIB__

Defined if-mdouble= acts as a multilib option.

__HAVE_DOUBLE32__

__HAVE_DOUBLE64__

Defined if the compiler supports 32-bit double resp. 64-bit double.The actual layout is specified by option-mdouble=.

__DEFAULT_DOUBLE__

The size in bits ofdouble if-mdouble= is not set.To test the layout ofdouble in a program, use the built-inmacro__SIZEOF_DOUBLE__.

__HAVE_LONG_DOUBLE32__

__HAVE_LONG_DOUBLE64__

__HAVE_LONG_DOUBLE_MULTILIB__

__DEFAULT_LONG_DOUBLE__

Same as above, but forlong double instead ofdouble.

__WITH_DOUBLE_COMPARISON__

Reflects the--with-double-comparison={tristate|bool|libf7}configure optionand is defined to2 or3.

__WITH_LIBF7_LIBGCC__

__WITH_LIBF7_MATH__

__WITH_LIBF7_MATH_SYMBOLS__

Reflects the--with-libf7={libgcc|math|math-symbols}configure option.

3.21.6.5 AVR Internal Options ¶

The following options are used internally by the compiler and to communicatebetween device specs files and the compiler proper. You don’t need to set theseoptions by hand, in particular they are not optimization options.Using these options in the wrong way may lead to sub-optimal or wrong code.They are documented for completeness, and in order to get a betterunderstanding ofdevice specsfiles.

-mn-flash=num ¶

Assume that the flash memory has a size ofnum times 64 KiB.This determines which__flashN address spaces are available.

-mflmap ¶

The device has theFLMAP bit field located in special functionregisterNVMCTRL_CTRLB.

-mrmw ¶

Assume that the device supports the Read-Modify-WriteinstructionsXCH,LAC,LAS andLAT.

-mshort-calls ¶

Assume thatRJMP andRCALL can target the wholeprogram memory. This option is used for multilib generation and selectionfor the devices from architectureavrxmega3.

-mskip-bug ¶

Generate code without skips (CPSE,SBRS,SBRC,SBIS,SBIC) over 32-bit instructions.

-msp8 ¶

Treat the stack pointer register as an 8-bit register,i.e. assume the high byte of the stack pointer is zero.This option is used by the compiler to select andbuild multilibs for architecturesavr2 andavr25.These architectures mix devices with and withoutSPH.