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The following options control the architecture variant for which codeis being compiled:
-mbarrel-shifter ¶Generate instructions supported by barrel shifter. This is the defaultunless-mcpu=ARC601 or ‘-mcpu=ARCEM’ is in effect.
-mjli-always ¶Force to call a function using jli_s instruction. This option isvalid only for ARCv2 architecture.
-mcpu=cpu ¶Set architecture type, register usage, and instruction schedulingparameters forcpu. There are also shortcut alias optionsavailable for backward compatibility and convenience. Supportedvalues forcpu are
Compile for ARC600. Aliases:-mA6,-mARC600.
Compile for ARC601. Alias:-mARC601.
Compile for ARC700. Aliases:-mA7,-mARC700.This is the default when configured with--with-cpu=arc700.
Compile for ARC EM.
Compile for ARC HS.
Compile for ARC EM CPU with no hardware extensions.
Compile for ARC EM4 CPU.
Compile for ARC EM4 DMIPS CPU.
Compile for ARC EM4 DMIPS CPU with the single-precision floating-pointextension.
Compile for ARC EM4 DMIPS CPU with single-precision floating-point anddouble assist instructions.
Compile for ARC HS CPU with no hardware extensions except the atomicinstructions.
Compile for ARC HS34 CPU.
Compile for ARC HS38 CPU.
Compile for ARC HS38 CPU with all hardware extensions on.
Compile for ARC HS4x CPU.
Compile for ARC HS4xD CPU.
Compile for ARC HS4x CPU release 3.10a.
Compile for ARC 600 CPU withnorm instructions enabled.
Compile for ARC 600 CPU withnorm and 32x16-bit multiplyinstructions enabled.
Compile for ARC 600 CPU withnorm andmul64-familyinstructions enabled.
Compile for ARC 601 CPU withnorm instructions enabled.
Compile for ARC 601 CPU withnorm and 32x16-bit multiplyinstructions enabled.
Compile for ARC 601 CPU withnorm andmul64-familyinstructions enabled.
Compile for ARC 700 on NPS400 chip.
Compile for ARC EM minimalist configuration featuring reduced registerset.
-mdpfp ¶-mdpfp-compactGenerate double-precision FPX instructions, tuned for the compactimplementation.
-mdpfp-fast ¶Generate double-precision FPX instructions, tuned for the fastimplementation.
-mno-dpfp-lrsr ¶-mdpfp-lrsrControl whetherlr andsr instructions use FPX extensionaux registers. This is enabled by default.
-mea ¶Generate extended arithmetic instructions. Currently onlydivaw,adds,subs, andsat16 aresupported. Only valid for-mcpu=ARC700.
-mmul32x16 ¶Generate 32x16-bit multiply and multiply-accumulate instructions.
-mmul64 ¶Generatemul64 andmulu64 instructions.Only valid for-mcpu=ARC600.
-mnorm ¶Generatenorm instructions. This is the default if-mcpu=ARC700is in effect.
-mspfp ¶-mspfp-compactGenerate single-precision FPX instructions, tuned for the compactimplementation.
-mspfp-fast ¶Generate single-precision FPX instructions, tuned for the fastimplementation.
-msimd ¶Enable generation of ARC SIMD instructions via target-specificbuiltins. Only valid for-mcpu=ARC700.
-msoft-float ¶This option ignored; it is provided for compatibility purposes only.Software floating-point code is emitted by default, and this defaultcan overridden by FPX options;-mspfp,-mspfp-compact, or-mspfp-fast for single precision, and-mdpfp,-mdpfp-compact, or-mdpfp-fast for double precision.
-mswap ¶Generateswap instructions.
-matomic ¶This enables use of the locked load/store conditional extension to implementatomic memory built-in functions. Not available for ARC 6xx or ARCEM cores.
-mdiv-rem ¶Enablediv andrem instructions for ARCv2 cores.
-mcode-density ¶-mno-code-densityEnable code density instructions for ARC EM.This option is on by default for ARC HS.
-mll64 ¶Enable double load/store operations for ARC HS cores.
-mtp-regno=regno ¶Specify thread pointer register number.
-mbitops ¶Enable use of NPS400 bit operations.
-mcmem ¶Enable use of NPS400 xld/xst extension.
-mmpy-option=multo ¶Compile ARCv2 code with a multiplier design option. You can specifythe option using either a string or numeric value formulto.‘wlh1’ is the default value. The recognized values are:
No multiplier available.
16x16 multiplier, fully pipelined.The following instructions are enabled:mpyw andmpyuw.
32x32 multiplier, fullypipelined (1 stage). The following instructions are additionallyenabled:mpy,mpyu,mpym,mpymu, andmpy_s.
32x32 multiplier, fully pipelined(2 stages). The following instructions are additionally enabled:mpy,mpyu,mpym,mpymu, andmpy_s.
Two 16x16 multipliers, blocking,sequential. The following instructions are additionally enabled:mpy,mpyu,mpym,mpymu, andmpy_s.
One 16x16 multiplier, blocking,sequential. The following instructions are additionally enabled:mpy,mpyu,mpym,mpymu, andmpy_s.
One 32x4 multiplier, blocking,sequential. The following instructions are additionally enabled:mpy,mpyu,mpym,mpymu, andmpy_s.
ARC HS SIMD support.
ARC HS SIMD support.
ARC HS SIMD support.
This option is only available for ARCv2 cores.
-mfpu=fpu ¶Enables support for specific floating-point hardware extensions for ARCv2cores. Supported values forfpu are:
Enables support for single-precision floating-point hardwareextensions.
Enables support for double-precision floating-point hardwareextensions. The single-precision floating-point extension is alsoenabled. Not available for ARC EM.
Enables support for double-precision floating-point hardwareextensions using double-precision assist instructions. The single-precisionfloating-point extension is also enabled. This option isonly available for ARC EM.
Enables support for double-precision floating-point hardwareextensions using double-precision assist instructions.The single-precision floating-point, square-root, and divideextensions are also enabled. This option isonly available for ARC EM.
Enables support for double-precision floating-point hardwareextensions using double-precision assist instructions.The single-precision floating-point and fused multiply and addhardware extensions are also enabled. This option isonly available for ARC EM.
Enables support for double-precision floating-point hardwareextensions using double-precision assist instructions.All single-precision floating-point hardware extensions are alsoenabled. This option is only available for ARC EM.
Enables support for single-precision floating-point, square-root and dividehardware extensions.
Enables support for double-precision floating-point, square-root and dividehardware extensions. This optionincludes option ‘fpus_div’. Not available for ARC EM.
Enables support for single-precision floating-point andfused multiply and add hardware extensions.
Enables support for double-precision floating-point andfused multiply and add hardware extensions. This optionincludes option ‘fpus_fma’. Not available for ARC EM.
Enables support for all single-precision floating-point hardwareextensions.
Enables support for all single- and double-precision floating-pointhardware extensions. Not available for ARC EM.
-mirq-ctrl-saved=register-range,blink,lp_count ¶Specifies general-purposes registers that the processor automaticallysaves/restores on interrupt entry and exit.register-range isspecified as two registers separated by a dash. The register rangealways starts withr0, the upper limit isfp register.blink andlp_count are optional. This option is onlyvalid for ARC EM and ARC HS cores.
-mrgf-banked-regs=number ¶Specifies the number of registers replicated in second register bankon entry to fast interrupt. Fast interrupts are interrupts with thehighest priority level P0. These interrupts save only PC and STATUS32registers to avoid memory transactions during interrupt entry and exitsequences. Use this option when you are using fast interrupts in anARC V2 family processor. Permitted values are 4, 8, 16, and 32.
-mlpc-width=width ¶Specify the width of thelp_count register. Valid values forwidth are 8, 16, 20, 24, 28 and 32 bits. The default width isfixed to 32 bits. If the width is less than 32, the compiler does notattempt to transform loops in your program to use the zero-delay loopmechanism unless it is known that thelp_count register canhold the required loop-counter value. Depending on the widthspecified, the compiler and run-time library might continue to use theloop mechanism for various needs. This option defines macro__ARC_LPC_WIDTH__ with the value ofwidth.
-mrf16 ¶This option instructs the compiler to generate code for a 16-entryregister file. This option defines the__ARC_RF16__preprocessor macro.
-mbranch-index ¶Enable use ofbi orbih instructions to implement jumptables.
The following options are passed through to the assembler, and alsodefine preprocessor macro symbols.
-mlock ¶Passed down to the assembler to enable the locked load/storeconditional extension. Also sets the preprocessor symbol__Xlock.
-mswape ¶Passed down to the assembler to enable the swap byte orderingextension instruction. Also sets the preprocessor symbol__Xswape.
-mxy ¶Passed down to the assembler to enable the XY memory extension. Alsosets the preprocessor symbol__Xxy.
The following options control how the assembly code is annotated:
-misize ¶Annotate assembler instructions with estimated addresses.
The following options are passed through to the linker:
-marclinux ¶-mno-arclinuxPassed through to the linker, to specify use of thearclinux emulation.This option is enabled by default in tool chains built forarc-linux-uclibc andarceb-linux-uclibc targetswhen profiling is not requested.
-marclinux_prof ¶-mno-arclinux_profPassed through to the linker, to specify use of thearclinux_prof emulation. This option is enabled by default intool chains built forarc-linux-uclibc andarceb-linux-uclibc targets when profiling is requested.
The following options control the semantics of generated code:
-mlong-calls ¶Generate calls as register indirect calls, thus providing accessto the full 32-bit address range.
-mmedium-calls ¶-mno-medium-callsDon’t use less than 25-bit addressing range for calls, which is theoffset available for an unconditional branch-and-linkinstruction. Conditional execution of function calls is suppressed, toallow use of the 25-bit range, rather than the 21-bit range withconditional branch-and-link. This is the default for tool chains builtforarc-linux-uclibc andarceb-linux-uclibc targets.
-Gnum ¶Put definitions of externally-visible data in a small data section ifthat data is no bigger thannum bytes. The default value ofnum is 4 for any ARC configuration, or 8 when we have doubleload/store operations.
-mno-sdata ¶Do not generate sdata references. This is the default for tool chainsbuilt forarc-linux-uclibc andarceb-linux-uclibctargets.
-mvolatile-cache ¶-mno-volatile-cacheControl how volatile references are accessed.The default is-mvolatile-cache, which uses ordinarycached memory accesses for volatile references.Use-mno-volatile-cache toenable cache bypass for volatile references.
The following options fine tune code generation:
-mauto-modify-reg ¶Enable the use of pre/post modify with register displacement.
-mno-brcc ¶-mbrccThis option controls a target-specific pass inarc_reorg togenerate compare-and-branch (brcc) instructions, whichis enabled by default.It has no effect ongeneration of these instructions driven by the combiner pass.
-mcase-vector-pcrel ¶Use PC-relative switch case tables to enable case table shortening.This is the default for-Os.
-mno-cond-exec ¶Disable the ARCompact-specific pass to generate conditionalexecution instructions.
Due to delay slot scheduling and interactions between operand numbers,literal sizes, instruction lengths, and the support for conditional execution,the target-independent pass to generate conditional execution is often lacking,so the ARC port has kept a special pass around that tries to find moreconditional execution generation opportunities after register allocation,branch shortening, and delay slot scheduling have been done. This passgenerally, but not always, improves performance and code size, at the cost ofextra compilation time, which is why there is an option to switch it off.If you have a problem with call instructions exceeding their allowableoffset range because they are conditionalized, you should consider using-mmedium-calls instead.
-mearly-cbranchsi ¶Enable pre-reload use of thecbranchsi pattern.
-mindexed-loads ¶Enable the use of indexed loads. This can be problematic because someoptimizers then assume that indexed stores exist, which is notthe case.
-mlra-priority-none ¶Don’t indicate any priority for target registers.
-mlra-priority-compact ¶Indicate target register priority for r0..r3 / r12..r15.
-mlra-priority-noncompact ¶Reduce target register priority for r0..r3 / r12..r15.
-mmillicode ¶When optimizing for size (using-Os), prologues and epiloguesthat have to save or restore a large number of registers are oftenshortened by using call to a special function in libgcc; this isreferred to as amillicode call. As these calls can poseperformance issues, and/or cause linking issues when linking in anonstandard way, this option is provided to turn on or off millicodecall generation.
-mcode-density-frame ¶This option enable the compiler to emitenter andleaveinstructions. These instructions are only valid for CPUs withcode-density feature.
-msize-level=level ¶Fine-tune size optimization with regards to instruction lengths and alignment.The recognized values forlevel are:
No size optimization. This level is deprecated and treated like ‘1’.
Short instructions are used opportunistically.
In addition, alignment of loops and of code after barriers are dropped.
In addition, optional data alignment is dropped, and the optionOs is enabled.
This defaults to ‘3’ when-Os is in effect. Otherwise,the behavior when this is not set is equivalent to level ‘1’.
-mtune=cpu ¶Set instruction scheduling parameters forcpu, overriding any impliedby-mcpu=.
Supported values forcpu are
Tune for ARC600 CPU.
Tune for ARC601 CPU.
Tune for ARC700 CPU with standard multiplier block.
Tune for ARC700 CPU with XMAC block.
Tune for ARC725D CPU.
Tune for ARC750D CPU.
Tune for ARCv2 core3 type CPU. This option enable usage ofdbnz instruction.
Tune for ARC4x release 3.10a.
-mmultcost=num ¶Cost to assume for a multiply instruction, with ‘4’ being equal to anormal instruction.
Next:ARM Options, Previous:AMD GCN Options, Up:Machine-Dependent Options [Contents][Index]