These options are defined for AArch64 implementations:
-mabi=name ¶Generate code for the specified data model. Permissible valuesare ‘ilp32’ for SysV-like data model where int, long int and pointersare 32 bits, and ‘lp64’ for SysV-like data model where int is 32 bits,but long int and pointers are 64 bits.
The default depends on the specific target configuration. Note thatthe LP64 and ILP32 ABIs are not link-compatible; you must compile yourentire program with the same ABI, and link with a compatible set of libraries.
The ‘ilp32’ model is deprecated.
-mbig-endian ¶Generate big-endian code. This is the default when GCC is configured for an‘aarch64_be-*-*’ target.
-mlittle-endian ¶Generate little-endian code. This is the default when GCC is configured for an‘aarch64-*-*’ but not an ‘aarch64_be-*-*’ target.
-menable-sysreg-checking ¶Generates an error message if an attempt is made to access a system registerwhich is not available on the target architecture.
-mgeneral-regs-only ¶Generate code that uses only the general-purpose registers. This preventsthe compiler from using floating-point and Advanced SIMD registers but does notimpose any restrictions on the assembler.
-mcmodel=tiny ¶Generate code for the tiny code model. The program and its statically definedsymbols must be within 1MB of each other. Programs can be statically ordynamically linked.
-mcmodel=small ¶Generate code for the small code model. The program and its statically definedsymbols must be within 4GB of each other. Programs can be statically ordynamically linked. This is the default code model.
-mcmodel=large ¶Generate code for the large code model. This makes no assumptions aboutaddresses and sizes of sections. Programs can be statically linked only. The-mcmodel=large option is incompatible with-mabi=ilp32,-fpic and-fPIC.
-mtp=nameSpecify the system register to use as a thread pointer. The valid valuesare ‘tpidr_el0’, ‘tpidrro_el0’, ‘tpidr_el1’, ‘tpidr_el2’,‘tpidr_el3’. For backwards compatibility the aliases ‘el0’,‘el1’, ‘el2’, ‘el3’ are also accepted.The default setting is ‘tpidr_el0’. It is recommended to compile allcode intended to interoperate with the same value of this option to avoidaccessing a different thread pointer from the wrong exception level.
-mstrict-align ¶-mno-strict-alignAvoid or allow generating memory accesses that may not be aligned on a naturalobject boundary as described in the architecture specification.
-momit-leaf-frame-pointer ¶-mno-omit-leaf-frame-pointerOmit or keep the frame pointer in leaf functions. The former behavior is thedefault.
-mstack-protector-guard=guard ¶-mstack-protector-guard-reg=reg-mstack-protector-guard-offset=offsetGenerate stack protection code using canary atguard. Supportedlocations are ‘global’ for a global canary or ‘sysreg’ for acanary in an appropriate system register.
With the latter choice the options-mstack-protector-guard-reg=reg and-mstack-protector-guard-offset=offset furthermore specifywhich system register to use as base register for reading the canary,and from what offset from that base register. There is no defaultregister or offset as this is entirely for use within the Linuxkernel.
-mtls-dialect=desc ¶Use TLS descriptors as the thread-local storage mechanism for dynamic accessesof TLS variables. This is the default.
-mtls-dialect=traditional ¶Use traditional TLS as the thread-local storage mechanism for dynamic accessesof TLS variables.
-mtls-size=size ¶Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48.This option requires binutils 2.26 or newer.
-mfix-cortex-a53-835769 ¶-mno-fix-cortex-a53-835769Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.This involves inserting a NOP instruction between memory instructions and64-bit integer multiply-accumulate instructions. This flag will be ignored ifan architecture or cpu is specified on the command line which does not need theworkaround.
-mfix-cortex-a53-843419 ¶-mno-fix-cortex-a53-843419Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.This erratum workaround is made at link time and this will only pass thecorresponding flag to the linker. This flag will be ignored ifan architecture or cpu is specified on the command line which does not need theworkaround.
-mlow-precision-recip-sqrt ¶-mno-low-precision-recip-sqrtEnable or disable the reciprocal square root approximation.This option only has an effect if-ffast-math or-funsafe-math-optimizations is used as well. Enabling this reducesprecision of reciprocal square root results to about 16 bits forsingle precision and to 32 bits for double precision.
-mlow-precision-sqrt ¶-mno-low-precision-sqrtEnable or disable the square root approximation.This option only has an effect if-ffast-math or-funsafe-math-optimizations is used as well. Enabling this reducesprecision of square root results to about 16 bits forsingle precision and to 32 bits for double precision.If enabled, it implies-mlow-precision-recip-sqrt.
-mlow-precision-div ¶-mno-low-precision-divEnable or disable the division approximation.This option only has an effect if-ffast-math or-funsafe-math-optimizations is used as well. Enabling this reducesprecision of division results to about 16 bits forsingle precision and to 32 bits for double precision.
-mtrack-speculation ¶-mno-track-speculationEnable or disable generation of additional code to track speculativeexecution through conditional branches. The tracking state can thenbe used by the compiler when expanding calls to__builtin_speculation_safe_value to permit a more efficient codesequence to be generated.
-moutline-atomics ¶-mno-outline-atomicsEnable or disable calls to out-of-line helpers to implement atomic operations.These helpers will, at runtime, determine if the LSE instructions fromARMv8.1-A can be used; if not, they will use the load/store-exclusiveinstructions that are present in the base ARMv8.0 ISA.
This option is only applicable when compiling for the base ARMv8.0instruction set. If using a later revision, e.g.-march=armv8.1-aor-march=armv8-a+lse, the ARMv8.1-Atomics instructions will beused directly. The same applies when using-mcpu= when theselected cpu supports the ‘lse’ feature.This option is on by default.
-mmax-vectorization ¶-mno-max-vectorizationEnable or disable an override to vectorizer cost model making vectorizationalways appear profitable. This option can be combined with-mautovec-preference allowing precise control over which ISA will beused for auto-vectorization. Unlike-fno-vect-cost-model or-fvect-cost-model=unlimited this option does not turn off costcomparison between different vector modes.
-mautovec-preference=name ¶Force an ISA selection strategy for auto-vectorization. The possiblevalues ofname are:
Use the default heuristics.
Use only Advanced SIMD for auto-vectorization.
Use only SVE for auto-vectorization.
Use both Advanced SIMD and SVE. Prefer Advanced SIMD when the costs aredeemed equal.
Use both Advanced SIMD and SVE. Prefer SVE when the costs are deemed equal.
For best performance it is highly recommended to use-mcpu or-mtune instead. This parameter should only be used for codeexploration.
-march=name ¶Specify the name of the target architecture and, optionally, one ormore feature modifiers. This option has the form-march=arch{+[no]feature}*.
The table below summarizes the permissible values forarchand the features that they enable by default:
| arch value | Architecture | Includes by default |
|---|---|---|
| ‘armv8-a’ | Armv8-A | ‘+fp’, ‘+simd’ |
| ‘armv8.1-a’ | Armv8.1-A | ‘armv8-a’, ‘+crc’, ‘+lse’, ‘+rdma’ |
| ‘armv8.2-a’ | Armv8.2-A | ‘armv8.1-a’ |
| ‘armv8.3-a’ | Armv8.3-A | ‘armv8.2-a’, ‘+pauth’, ‘+fcma’, ‘+jscvt’ |
| ‘armv8.4-a’ | Armv8.4-A | ‘armv8.3-a’, ‘+flagm’, ‘+fp16fml’, ‘+dotprod’, ‘+rcpc2’ |
| ‘armv8.5-a’ | Armv8.5-A | ‘armv8.4-a’, ‘+sb’, ‘+ssbs’, ‘+predres’, ‘+frintts’, ‘+flagm2’ |
| ‘armv8.6-a’ | Armv8.6-A | ‘armv8.5-a’, ‘+bf16’, ‘+i8mm’ |
| ‘armv8.7-a’ | Armv8.7-A | ‘armv8.6-a’, ‘+wfxt’, ‘+xs’ |
| ‘armv8.8-a’ | Armv8.8-a | ‘armv8.7-a’, ‘+mops’ |
| ‘armv8.9-a’ | Armv8.9-a | ‘armv8.8-a’ |
| ‘armv9-a’ | Armv9-A | ‘armv8.5-a’, ‘+sve’, ‘+sve2’ |
| ‘armv9.1-a’ | Armv9.1-A | ‘armv9-a’, ‘+bf16’, ‘+i8mm’ |
| ‘armv9.2-a’ | Armv9.2-A | ‘armv9.1-a’, ‘+wfxt’, ‘+xs’ |
| ‘armv9.3-a’ | Armv9.3-A | ‘armv9.2-a’, ‘+mops’ |
| ‘armv9.4-a’ | Armv9.4-A | ‘armv9.3-a’, ‘+sve2p1’ |
| ‘armv9.5-a’ | Armv9.5-A | ‘armv9.4-a’, ‘cpa’, ‘+faminmax’, ‘+lut’ |
| ‘armv8-r’ | Armv8-R | ‘armv8-r’ |
The value ‘native’ is available on native AArch64 GNU/Linux andcauses the compiler to pick the architecture of the host system. Thisoption has no effect if the compiler is unable to recognize thearchitecture of the host system. When-march=native is given andno other-mcpu or-mtune is given then GCC will pickthe host CPU as the CPU to tune for as well as select the architecture featuresfrom. That is,-march=native is treated as-mcpu=native.
The permissible values forfeature are listed in the sub-sectionon-march and-mcpuFeature Modifiers. Where conflicting feature modifiers arespecified, the right-most feature is used.
GCC usesname to determine what kind of instructions it can emitwhen generating assembly code. If-march is specifiedwithout either of-mtune or-mcpu also beingspecified, the code is tuned to perform well across a range of targetprocessors implementing the target architecture.
-mtune=name ¶Specify the name of the target processor for which GCC should tune theperformance of the code. Permissible values for this option are:‘generic’, ‘cortex-a35’, ‘cortex-a53’, ‘cortex-a55’,‘cortex-a57’, ‘cortex-a72’, ‘cortex-a73’, ‘cortex-a75’,‘cortex-a76’, ‘cortex-a76ae’, ‘cortex-a77’,‘cortex-a65’, ‘cortex-a65ae’, ‘cortex-a34’,‘cortex-a78’, ‘cortex-a78ae’, ‘cortex-a78c’,‘ares’, ‘exynos-m1’, ‘emag’, ‘falkor’,‘oryon-1’,‘neoverse-512tvb’, ‘neoverse-e1’, ‘neoverse-n1’,‘neoverse-n2’, ‘neoverse-v1’, ‘neoverse-v2’, ‘grace’,‘neoverse-v3’, ‘neoverse-v3ae’, ‘neoverse-n3’, ‘olympus’,‘cortex-a725’, ‘cortex-x925’,‘qdf24xx’, ‘saphira’, ‘phecda’, ‘xgene1’, ‘vulcan’,‘octeontx’, ‘octeontx81’, ‘octeontx83’,‘octeontx2’, ‘octeontx2t98’, ‘octeontx2t96’‘octeontx2t93’, ‘octeontx2f95’, ‘octeontx2f95n’,‘octeontx2f95mm’,‘a64fx’, ‘fujitsu-monaka’,‘thunderx’, ‘thunderxt88’,‘thunderxt88p1’, ‘thunderxt81’, ‘tsv110’, ‘hip12’,‘thunderxt83’, ‘thunderx2t99’, ‘thunderx3t110’, ‘zeus’,‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’,‘cortex-a73.cortex-a35’, ‘cortex-a73.cortex-a53’,‘cortex-a75.cortex-a55’, ‘cortex-a76.cortex-a55’,‘cortex-r82’, ‘cortex-r82ae’, ‘cortex-x1’, ‘cortex-x1c’,‘cortex-x2’, ‘cortex-x3’, ‘cortex-x4’, ‘cortex-a510’,‘cortex-a520’, ‘cortex-a520ae’, ‘cortex-a710’, ‘cortex-a715’,‘cortex-a720’, ‘cortex-a720ae’, ‘ampere1’, ‘ampere1a’,‘ampere1b’, ‘ampere1c’, ‘cobalt-100’, ‘apple-m1’,‘apple-m2’, ‘apple-m3’, ‘apple-m4’, ‘c1-nano’,‘c1-pro’, ‘c1-premium’ ‘c1-ultra’ and ‘native’.
The values ‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’,‘cortex-a73.cortex-a35’, ‘cortex-a73.cortex-a53’,‘cortex-a75.cortex-a55’, ‘cortex-a76.cortex-a55’,‘apple-m1’, ‘apple-m2’, ‘apple-m3’, ‘gb10’ specify that GCCshould tune for a big.LITTLE system.
The value ‘neoverse-512tvb’ specifies that GCC should tunefor Neoverse cores that (a) implement SVE and (b) have a total vectorbandwidth of 512 bits per cycle. In other words, the option tells GCC totune for Neoverse cores that can execute 4 128-bit Advanced SIMD arithmeticinstructions a cycle and that can execute an equivalent number of SVEarithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit SVE).This is more general than tuning for a specific core like Neoverse V1but is more specific than the default tuning described below.
Additionally on native AArch64 GNU/Linux systems the value‘native’ tunes performance to the host system. This option has no effectif the compiler is unable to recognize the processor of the host system.
Where none of-mtune=,-mcpu= or-march=are specified, the code is tuned to perform well across a rangeof target processors.
This option cannot be suffixed by feature modifiers.
-mcpu=name ¶Specify the name of the target processor, optionally suffixed by oneor more feature modifiers. This option has the form-mcpu=cpu{+[no]feature}*, wherethe permissible values forcpu are the same as those availablefor-mtune. The permissible values forfeature aredocumented in the sub-section on-march and-mcpuFeature Modifiers. Where conflicting feature modifiers arespecified, the right-most feature is used.
GCC usesname to determine what kind of instructions it can emit whengenerating assembly code (as if by-march) and to determinethe target processor for which to tune for performance (as ifby-mtune). Where this option is used in conjunctionwith-march or-mtune, those options take precedenceover the appropriate part of this option.
-mcpu=neoverse-512tvb is special in that it does not referto a specific core, but instead refers to all Neoverse cores that(a) implement SVE and (b) have a total vector bandwidth of 512 bitsa cycle. Unless overridden by-march,-mcpu=neoverse-512tvb generates code that can run on aNeoverse V1 core, since Neoverse V1 is the first Neoverse core withthese properties. Unless overridden by-mtune,-mcpu=neoverse-512tvb tunes code in the same way as for-mtune=neoverse-512tvb.
-moverride=string ¶Override tuning decisions made by the back-end in response to a-mtune= switch. The syntax, semantics, and accepted valuesforstring in this option are not guaranteed to be consistentacross releases.
This option is only intended to be useful when developing GCC.
-mpc-relative-literal-loads ¶-mno-pc-relative-literal-loadsEnable or disable PC-relative literal loads. With this option literal pools areaccessed using a single instruction and emitted after each function. Thislimits the maximum size of functions to 1MB. This is enabled by default for-mcmodel=tiny.
-msign-return-address=scope ¶Select the function scope on which return address signing will be applied.Permissible values are ‘none’, which disables return address signing,‘non-leaf’, which enables pointer signing for functions which are not leaffunctions, and ‘all’, which enables pointer signing for all functions. Thedefault value is ‘none’. This option has been deprecated by-mbranch-protection.
-mbranch-protection=features ¶Select the branch protection features to use.features can have one of the following forms:
‘none’ is the default and turns off all types of branch protection.
‘standard’ turns on all types of branch protection features. If a featurehas additional tuning options, then ‘standard’ sets it to its standardlevel.
‘pac-ret’ turns on return address signing to its standardlevel: signing functions that save the return address to memory (non-leaffunctions practically always do this) using the A-key.
‘pac-ret+leaf’ extends the ‘pac-ret’ signing to include leaffunctions.
‘pac-ret+b-key’ or ‘pac-ret+leaf+b-key’ can be used tosign the functions with the B-key instead of the A-key.
‘bti’ turns on branch target identification mechanism.
‘gcs’ turns on guarded control stack compatible code generation.
-mharden-sls=opts ¶Enable compiler hardening against straight line speculation (SLS).opts is a comma-separated list of the following options:
In addition, ‘-mharden-sls=all’ enables all SLS hardening while‘-mharden-sls=none’ disables all SLS hardening.
-mearly-ra=scope ¶Determine when to enable an early register allocation pass. This pass runsbefore instruction scheduling and tries to find a spill-free allocation offloating-point and vector code. It also tries to make use of stridedmulti-register instructions, such as SME2’s strided LD1 and ST1.
The possible values ofscope are:all, which runs the pass onall functions;strided, which runs the pass on functions that haveaccess to strided multi-register instructions; andnone, whichdisables the pass.
-mearly-ra=all is the default for-O2 and above, and for-Os.-mearly-ra=none is the default otherwise.
-mearly-ldp-fusion ¶-mno-early-ldp-fusionEnable the copy of the AArch64 load/store pair fusion pass that runs beforeregister allocation. Enabled by default at ‘-O’ and above.
-mlate-ldp-fusion ¶-mno-late-ldp-fusionEnable the copy of the AArch64 load/store pair fusion pass that runs afterregister allocation. Enabled by default at ‘-O’ and above.
-msve-vector-bits=bits ¶Specify the number of bits in an SVE vector register. This option only hasan effect when SVE is enabled.
GCC supports two forms of SVE code generation: “vector-lengthagnostic” output that works with any size of vector register and“vector-length specific” output that allows GCC to make assumptionsabout the vector length when it is useful for optimization reasons.The possible values of ‘bits’ are: ‘scalable’, ‘128’,‘256’, ‘512’, ‘1024’ and ‘2048’.Specifying ‘scalable’ selects vector-length agnosticoutput. At present ‘-msve-vector-bits=128’ also generates vector-lengthagnostic output for big-endian targets. All other values generatevector-length specific code. The behavior of these values may changein future releases and no value except ‘scalable’ should berelied on for producing code that is portable across differenthardware SVE vector lengths.
The default is ‘-msve-vector-bits=scalable’, which producesvector-length agnostic code.
Feature modifiers used with-march and-mcpu can be any ofthe following and their inversesnofeature:
Enable CRC extension. This is on by default for-march=armv8.1-a.
Enable Crypto extension. This also enables Advanced SIMD and floating-pointinstructions.
Enable floating-point instructions. This is on by default for all possiblevalues for options-march and-mcpu.
Enable Advanced SIMD instructions. This also enables floating-pointinstructions. This is on by default for all possible values for options-march and-mcpu.
Enable Scalable Vector Extension instructions. This also enables AdvancedSIMD and floating-point instructions.
Enable Large System Extension instructions. This is on by default for-march=armv8.1-a.
Enable Round Double Multiply Accumulate instructions. This is on by defaultfor-march=armv8.1-a.
Enable FP16 extension. This also enables floating-point instructions.
Enable FP16 fmla extension. This also enables FP16 extensions andfloating-point instructions. This option is enabled by default for-march=armv8.4-a. Use of this option with architectures prior to Armv8.2-A is not supported.
Enable the RCpc extension. This enables the use of the LDAPR instructions forload-acquire atomic semantics, and passes it on to the assembler, enablinginline asm statements to use instructions from the RCpc extension.
Enable the Dot Product extension. This also enables Advanced SIMD instructions.
Enable the Armv8-a aes and pmull crypto extension. This also enables AdvancedSIMD instructions.
Enable the Armv8-a sha2 crypto extension. This also enables Advanced SIMD instructions.
Enable the sha512 and sha3 crypto extension. This also enables Advanced SIMDinstructions. Use of this option with architectures prior to Armv8.2-A is not supported.
Enable the sm3 and sm4 crypto extension. This also enables Advanced SIMD instructions.Use of this option with architectures prior to Armv8.2-A is not supported.
Enable the Statistical Profiling extension. This option is only to enable theextension at the assembler level and does not affect code generation.
Enable the Armv8.5-a Random Number instructions. This option is only toenable the extension at the assembler level and does not affect codegeneration.
Enable the Armv8.5-a Memory Tagging Extensions.Use of this option with architectures prior to Armv8.5-A is not supported.
Enable the Armv8-a Speculation Barrier instruction. This option is only toenable the extension at the assembler level and does not affect codegeneration. This option is enabled by default for-march=armv8.5-a.
Enable the Armv8-a Speculative Store Bypass Safe instruction. This optionis only to enable the extension at the assembler level and does not affect codegeneration. This option is enabled by default for-march=armv8.5-a.
Enable the Armv8-a Execution and Data Prediction Restriction instructions.This option is only to enable the extension at the assembler level and doesnot affect code generation. This option is enabled by default for-march=armv8.5-a.
Enable the Armv8-a Scalable Vector Extension 2. This also enables SVEinstructions.
Enable SVE2 bitperm instructions. This also enables SVE2 instructions.
Enable SVE2 sm4 instructions. This also enables SVE2 instructions.
Enable SVE2 aes instructions. This also enables SVE2 instructions.
Enable SVE2 sha3 instructions. This also enables SVE2 instructions.
Enable SVE2.1 instructions. This also enables SVE2 instructions.
Enable the Transactional Memory Extension.
Enable 8-bit Integer Matrix Multiply instructions. This also enablesAdvanced SIMD and floating-point instructions. This option is enabled bydefault for-march=armv8.6-a. Use of this option with architecturesprior to Armv8.2-A is not supported.
Enable 32-bit Floating point Matrix Multiply instructions. This also enablesSVE instructions. Use of this option with architectures prior to Armv8.2-A isnot supported.
Enable 64-bit Floating point Matrix Multiply instructions. This also enablesSVE instructions. Use of this option with architectures prior to Armv8.2-A isnot supported.
Enable brain half-precision floating-point instructions. This also enablesAdvanced SIMD and floating-point instructions. This option is enabled bydefault for-march=armv8.6-a. Use of this option with architecturesprior to Armv8.2-A is not supported.
Enable the 64-byte atomic load and store instructions for accelerators.
Enable the instructions to accelerate memory operations likememcpy,memmove,memset. This option is enabled by default for-march=armv8.8-a
Enable the Flag Manipulation instructions Extension.
Enable the FlagM2 flag conversion instructions.
Enable the Pointer Authentication Extension.
Enable the Common Short Sequence Compression instructions.
Enable the shorter compare and branch instructions,cbb,cbh andcb.
Enable the Scalable Matrix Extension. This is only supported when SVE2 is alsoenabled.
Enable the FEAT_SME_I16I64 extension to SME. This also enables SMEinstructions.
Enable the FEAT_SME_F64F64 extension to SME. This also enables SMEinstructions.
Enable the Scalable Matrix Extension 2. This also enables SME instructions.
Enable the FEAT_SME_F8F16 extension to SME. This also enables SME2 and FP8instructions.
Enable the FEAT_SME_F8F32 extension to SME. This also enables SME2 and FP8instructions.
Enable the FEAT_SME_B16B16 extension to SME. This also enables SME2and SVE_B16B16 instructions.
Enable the FEAT_SME_F16F16 extension to SME. This also enables SME2instructions.
Enable the Scalable Matrix Extension version 2.1. This also enables SME2instructions.
Enable the complex number SIMD extensions.
Enable thefjcvtzs JavaScript conversion instruction.
Enable floating-point round to integral value instructions.
Enablewfet andwfit instructions.
Enable the XS memory attribute extension.
Enable the LSE128 128-bit atomic instructions extension. This alsoenables LSE instructions.
Enable support for 128-bit system register read/write instructions.This also enables the LSE128 extension.
Enable support for Armv9.4-a Guarded Control Stack extension.
Enable support for Armv8.9-a/9.4-a translation hardening extension.
Enable the RCpc2 extension.
Enable the RCpc3 (Release Consistency) extension.
Enable the fp8 (8-bit floating point) extension.
Enable the fp8 (8-bit floating point) multiply accumulate extension.
Enable the fp8 (8-bit floating point) multiply accumulate extension in streamingmode.
Enable the fp8 (8-bit floating point) to single-precision 4-way dot productextension.
Enable the fp8 (8-bit floating point) to single-precision 4-way dot productextension in streaming mode.
Enable the fp8 (8-bit floating point) to half-precision 2-way dot productextension.
Enable the fp8 (8-bit floating point) to half-precision 2-way dot productextension in streaming mode.
Enable the Floating Point Absolute Maximum/Minimum extension.
Enable the Lookup Table extension.
Enable the SME Lookup Table v2 (LUTv2) extension.
Enable the Checked Pointer Arithmetic instructions.
Enable the SVE non-widening brain floating-point (bf16) extension.This only has an effect whensve2 orsme2 are also enabled.
Enable the SVE_BFSCALE extension.
Featurecrypto impliesaes,sha2, andsimd,which impliesfp.Conversely,nofp impliesnosimd, which impliesnocrypto,noaes andnosha2.